Attachment #109 for bug #519

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Lines 18-26 develop: Link Here

(-)a/Makefile (-1 / +7 lines)
18	python3 src/soc/decoder/pseudo/pywriter.py	18	python3 src/soc/decoder/pseudo/pywriter.py
19		19
20	run_sim: install	20	run_sim: install
21	python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/libresoc.v	21	python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/\
		22	libresoc/libresoc.v
22	python3 src/soc/litex/florent/sim.py --cpu=libresoc	23	python3 src/soc/litex/florent/sim.py --cpu=libresoc
23		24
		25	testgpio_run_sim:
		26	python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/\
		27	libresoc.v --enable-testgpio
		28	python3 src/soc/litex/florent/sim.py --cpu=libresoc --variant=standardjtagtestgpio
		29
24	test: install	30	test: install
25	python3 setup.py test # could just run nosetest3...	31	python3 setup.py test # could just run nosetest3...




from litex.build.generic_platform import ConstraintManager


CPU_VARIANTS = ["standard", "standard32", "standardjtag",
                "standardjtagtestgpio", "ls180",
                "standardjtagnoirq"]



        jtag_en = ('jtag' in variant) or variant == 'ls180'

        if "testgpio" in variant:
            self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
        if jtag_en:
            self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)

            self.clk_sel = Signal(3)
            self.cpu_params['i_clk_sel_i'] = self.clk_sel
            self.cpu_params['o_pll_48_o'] = self.pll_48_o

        # add wishbone buses to cpu params
        self.cpu_params.update(make_wb_bus("ibus", ibus))
        self.cpu_params.update(make_wb_bus("dbus", dbus))
        self.cpu_params.update(make_wb_slave("ics_wb", ics))
        self.cpu_params.update(make_wb_slave("icp_wb", icp))
        if "testgpio" in variant:
            self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
        if jtag_en:
            self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))




# LibreSoCSim -----------------------------------------------------------------

class LibreSoCSim(SoCSDRAM):
    def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
            with_sdram=True,
            sdram_module          = "AS4C16M16",
            #sdram_data_width      = 16,
            #sdram_module          = "MT48LC16M16",

        platform     = Platform()
        sys_clk_freq = int(100e6)

        #cpu_data_width = 32
        cpu_data_width = 64

        if cpu_data_width == 32:
            variant = "standard32"
        else:
            variant = "standardjtag"

        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
        #            "hello_world/hello_world.bin"
        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \

            ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
            self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)

        if "gpio" in variant:
            # Simple GPIO peripheral
            gpio_addr = self.mem_map['gpio']
            gpio_wb = self.cpu.simple_gpio

    parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
    parser.add_argument("--cpu",          default="libresoc",
                        help="CPU to use: libresoc (default) or microwatt")
    parser.add_argument("--variant",      default="standardjtag",
                        help="Specify variant with different features")
    parser.add_argument("--debug",        action="store_true",
                        help="Enable debug traces")
    parser.add_argument("--trace",        action="store_true",

    sim_config.add_module("jtagremote", "jtag", args={'port': 44853})

    for i in range(2):
        soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
        builder = Builder(soc,compile_gateware = i!=0)
        builder.build(sim_config=sim_config,
            run         = i!=0,

Lines 38-43 if __name__ == '__main__': Link Here

(-)a/src/soc/simple/issuer_verilog.py (+7 lines)
38	'mul': 1,	38	'mul': 1,
39	'shiftrot': 1	39	'shiftrot': 1
40	}	40	}
		41
41	pspec = TestMemPspec(ldst_ifacetype='bare_wb',	42	pspec = TestMemPspec(ldst_ifacetype='bare_wb',
42	imem_ifacetype='bare_wb',	43	imem_ifacetype='bare_wb',
43	addr_wid=48,	44	addr_wid=48,
Lines 55-60 if __name__ == '__main__': Link Here
55	debug=args.debug, # set to jtag or dmi	56	debug=args.debug, # set to jtag or dmi
56	units=units)	57	units=units)
57		58
		59	print("nocore", pspec.__dict__["nocore"])
		60	print("gpio", pspec.__dict__["gpio"])
		61	print("xics", pspec.__dict__["xics"])
		62	print("use_pll", pspec.__dict__["use_pll"])
		63	print("debug", pspec.__dict__["debug"])
		64
58	dut = TestIssuer(pspec)	65	dut = TestIssuer(pspec)
59		66
60	vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")	67	vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")

Return to bug 519

Lines 13-19 from libresoc.ls180 import io Link Here

(-)a/src/soc/litex/florent/libresoc/core.py (-4 / +5 lines)
13	from litex.build.generic_platform import ConstraintManager	13	from litex.build.generic_platform import ConstraintManager
14		14
15		15
16	CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180",	16	CPU_VARIANTS = ["standard", "standard32", "standardjtag",
		17	"standardjtagtestgpio", "ls180",
17	"standardjtagnoirq"]	18	"standardjtagnoirq"]
18		19
Lines 167-173 class LibreSoC(CPU): Link Here
167		168
168	jtag_en = ('jtag' in variant) or variant == 'ls180'	169	jtag_en = ('jtag' in variant) or variant == 'ls180'
169		170
170	if "gpiotest" in variant:	171	if "testgpio" in variant:
171	self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)	172	self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
172	if jtag_en:	173	if jtag_en:
173	self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)	174	self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
Lines 235-247 class LibreSoC(CPU): Link Here
235	self.clk_sel = Signal(3)	236	self.clk_sel = Signal(3)
236	self.cpu_params['i_clk_sel_i'] = self.clk_sel	237	self.cpu_params['i_clk_sel_i'] = self.clk_sel
237	self.cpu_params['o_pll_48_o'] = self.pll_48_o	238	self.cpu_params['o_pll_48_o'] = self.pll_48_o
238		239
239	# add wishbone buses to cpu params	240	# add wishbone buses to cpu params
240	self.cpu_params.update(make_wb_bus("ibus", ibus))	241	self.cpu_params.update(make_wb_bus("ibus", ibus))
241	self.cpu_params.update(make_wb_bus("dbus", dbus))	242	self.cpu_params.update(make_wb_bus("dbus", dbus))
242	self.cpu_params.update(make_wb_slave("ics_wb", ics))	243	self.cpu_params.update(make_wb_slave("ics_wb", ics))
243	self.cpu_params.update(make_wb_slave("icp_wb", icp))	244	self.cpu_params.update(make_wb_slave("icp_wb", icp))
244	if "gpiotest" in variant:	245	if "testgpio" in variant:
245	self.cpu_params.update(make_wb_slave("gpio_wb", gpio))	246	self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
246	if jtag_en:	247	if jtag_en:
247	self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))	248	self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))

Lines 32-38 SoCCSRHandler.supported_address_width.append(12) Link Here

(-)a/src/soc/litex/florent/sim.py (-10 / +6 lines)
32	# LibreSoCSim -----------------------------------------------------------------	32	# LibreSoCSim -----------------------------------------------------------------
33		33
34	class LibreSoCSim(SoCSDRAM):	34	class LibreSoCSim(SoCSDRAM):
35	def __init__(self, cpu="libresoc", debug=False, with_sdram=True,	35	def __init__(self, cpu="libresoc", variant="standardjtag", debug=False,
		36	with_sdram=True,
36	sdram_module = "AS4C16M16",	37	sdram_module = "AS4C16M16",
37	#sdram_data_width = 16,	38	#sdram_data_width = 16,
38	#sdram_module = "MT48LC16M16",	39	#sdram_module = "MT48LC16M16",
Lines 43-56 class LibreSoCSim(SoCSDRAM): Link Here
43	platform = Platform()	44	platform = Platform()
44	sys_clk_freq = int(100e6)	45	sys_clk_freq = int(100e6)
45		46
46	#cpu_data_width = 32
47	cpu_data_width = 64
48
49	if cpu_data_width == 32:
50	variant = "standard32"
51	else:
52	variant = "standardjtag"
53
54	#ram_fname = "/home/lkcl/src/libresoc/microwatt/" \	47	#ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
55	# "hello_world/hello_world.bin"	48	# "hello_world/hello_world.bin"
56	#ram_fname = "/home/lkcl/src/libresoc/microwatt/" \	49	#ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
Lines 124-129 class LibreSoCSim(SoCSDRAM): Link Here
124	ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)	117	ics_region = SoCRegion(origin=ics_addr, size=0x1000, cached=False)
125	self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)	118	self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
126		119
		120	if "gpio" in variant:
127	# Simple GPIO peripheral	121	# Simple GPIO peripheral
128	gpio_addr = self.mem_map['gpio']	122	gpio_addr = self.mem_map['gpio']
129	gpio_wb = self.cpu.simple_gpio	123	gpio_wb = self.cpu.simple_gpio
Lines 451-456 def main(): Link Here
451	parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")	445	parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim")
452	parser.add_argument("--cpu", default="libresoc",	446	parser.add_argument("--cpu", default="libresoc",
453	help="CPU to use: libresoc (default) or microwatt")	447	help="CPU to use: libresoc (default) or microwatt")
		448	parser.add_argument("--variant", default="standardjtag",
		449	help="Specify variant with different features")
454	parser.add_argument("--debug", action="store_true",	450	parser.add_argument("--debug", action="store_true",
455	help="Enable debug traces")	451	help="Enable debug traces")
456	parser.add_argument("--trace", action="store_true",	452	parser.add_argument("--trace", action="store_true",
Lines 466-472 def main(): Link Here
466	sim_config.add_module("jtagremote", "jtag", args={'port': 44853})	462	sim_config.add_module("jtagremote", "jtag", args={'port': 44853})
467		463
468	for i in range(2):	464	for i in range(2):
469	soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)	465	soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant)
470	builder = Builder(soc,compile_gateware = i!=0)	466	builder = Builder(soc,compile_gateware = i!=0)
471	builder.build(sim_config=sim_config,	467	builder.build(sim_config=sim_config,
472	run = i!=0,	468	run = i!=0,