Attachment #111 for bug #519

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Line 1 Link Here

(-)a/libreriscv (-1 / +1 lines)
1	Subproject commit b4ace15028bbfac364e2082931e8d147dfd41c68	1	Subproject commit 2a70f55e1075ca3f17d255b98c3d6a42901db8fd




from soc.debug.jtag import Pins
from c4m.nmigen.jtag.tap import IOType

from ls180 import io
from litex.build.generic_platform import ConstraintManager


CPU_VARIANTS = ["standard", "standard32", "standardjtag",
                "standardjtagtestgpio", "ls180",
                "standardjtagnoirq"]


def make_wb_bus(prefix, obj, simple=False):
    res = {}
    outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']

        if f.endswith(name):
            return getattr(rec, f)


def make_jtag_ioconn(res, pin, cpupads, iopads):
    (fn, pin, iotype, pin_name, scan_idx) = pin
    #serial_tx__core__o, serial_rx__pad__i,

class LibreSoC(CPU):
    name                 = "libre_soc"
    human_name           = "Libre-SoC"
    variants             = CPU_VARIANTS
    endianness           = "little"
    gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
    linker_output_format = "elf64-powerpcle"

        flags += "-D__microwatt__ "
        return flags

    def __init__(self, platform, dmi=True, add_sources=True):
        self.platform     = platform
        self.variant      = variant
        self.reset        = Signal()
        self.interrupt    = Signal(16)

        self.data_width  = 64
        self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)

        if variant == "standard32":
            self.data_width           = 32
            self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
        else:
            self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
            self.data_width           = 64
        self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)

        self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
        self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)

        jtag_en = ('jtag' in variant) or variant == 'ls180'

        if "testgpio" in variant:
            self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
        if jtag_en:
            self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)

        self.periph_buses = [ibus, dbus]
        self.memory_buses = []

        if jtag_en:
            self.periph_buses.append(jtag_wb)
            self.jtag_tck = Signal(1)
            self.jtag_tms = Signal(1)
            self.jtag_tdi = Signal(1)
            self.jtag_tdo = Signal(1)
        else:
            self.dmi_addr = Signal(4)
            self.dmi_din = Signal(64)
            self.dmi_dout = Signal(64)
            self.dmi_wr = Signal(1)
            self.dmi_ack = Signal(1)
            self.dmi_req = Signal(1)

        # # #



        )

        # interrupts
        self.cpu_params['i_int_level_i'] = self.interrupt
            self.cpu_params['i_int_level_i'] = self.interrupt

        if dmi:
            self.dmi_addr = Signal(4)
            self.dmi_din = Signal(64)
            self.dmi_dout = Signal(64)
            self.dmi_wr = Signal(1)
            self.dmi_ack = Signal(1)
            self.dmi_req = Signal(1)
            ))
        else:
            self.cpu_params.update(dict(
                # DMI Debug bus
                i_dmi_addr_i          = self.dmi_addr,

                o_dmi_ack_o           = self.dmi_ack,
            ))

        # add clock select, pll output
        if variant == "ls180":
            self.pll_48_o = Signal()
            self.clk_sel = Signal(3)
            self.cpu_params['i_clk_sel_i'] = self.clk_sel
            self.cpu_params['o_pll_48_o'] = self.pll_48_o

        # add wishbone buses to cpu params
        self.cpu_params.update(make_wb_bus("ibus", ibus))
        self.cpu_params.update(make_wb_bus("dbus", dbus))
        self.cpu_params.update(make_wb_slave("ics_wb", ics))
        self.cpu_params.update(make_wb_slave("icp_wb", icp))
        if "testgpio" in variant:
            self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
        if jtag_en:
            self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))

        if variant == 'ls180':
            # urr yuk.  have to expose iopads / pins from core to litex
            # then back again.  cut _some_ of that out by connecting
            self.padresources = io()
            self.pad_cm = ConstraintManager(self.padresources, [])
            self.cpupads = {}
            iopads = {}
            litexmap = {}
            subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
                      'pwm', 'sd0', 'sdr'}
            for periph in subset:
                origperiph = periph
                num = None
                if periph[-1].isdigit():
                    periph, num = periph[:-1], int(periph[-1])
                print ("periph request", periph, num)
                if periph == 'mspi':
                    if num == 0:
                        periph, num = 'spimaster', None
                    else:
                        periph, num = 'spisdcard', None
                elif periph == 'sdr':
                    periph = 'sdram'
                elif periph == 'mtwi':
                    periph = 'i2c'
                elif periph == 'sd':
                    periph, num = 'sdcard', None
                litexmap[origperiph] = (periph, num)
                self.cpupads[origperiph] = platform.request(periph, num)
                iopads[origperiph] = self.pad_cm.request(periph, num)
                if periph == 'sdram':
                    # special-case sdram clock
                    ck = platform.request("sdram_clock")
                    self.cpupads['sdram_clock'] = ck
                    ck = self.pad_cm.request("sdram_clock")
                    iopads['sdram_clock'] = ck

            pinset = get_pinspecs(subset=subset)
            p = Pins(pinset)
            for pin in list(p):
                make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)

        if add_sources:
            # add verilog sources
            self.add_sources(platform)

    def set_reset_address(self, reset_address):
        assert not hasattr(self, "reset_address")

    def do_finalize(self):
        self.specials += Instance("test_issuer", **self.cpu_params)

class LS32(LibreSoC):
    def __init__(self):
        super().__init__(dbus=wb.Interface(data_width=64, adr_width=29))
        self.data_width = 32
        self.dbus = dbus = wb.Interface(data_width=self.data_width,
                                        adr_width=30)
        self.cpu_params.update(make_wb_bus("dbus", dbus))
        self.periph_buses[1] = dbus

class LSJTAG(LibreSoC):
    def __init__(self):
        super().__init__(dmi=False)
        self.jtag_tck = Signal(1)
        self.jtag_tms = Signal(1)
        self.jtag_tdi = Signal(1)
        self.jtag_tdo = Signal(1)
        self.cpu_params.update(dict(
            # JTAG Debug bus
            o_TAP_bus__tdo = self.jtag_tdo,
            i_TAP_bus__tdi = self.jtag_tdi,
            i_TAP_bus__tms = self.jtag_tms,
            i_TAP_bus__tck = self.jtag_tck,
        ))
        self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
        self.periph_buses.append(jtag_wb)
        self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))


class LSNoIRQ(LSJTAG):
    def __init__(self):
        super().__init__()
        del(self.interrupt)
        self.cpu_params.pop('i_int_level_i')

class LSGPIO(LSNoIRQ):
    def __init__(self):
        super().__init__()
        self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
        self.cpu_params.update(make_wb_slave("gpio_wb", gpio))

class LS180(LSJTAG):
    def __init__(self):
        super().__init__(add_sources=False)
        self.pll_48_o = Signal()
        self.clk_sel = Signal(3)
        self.cpu_params['i_clk_sel_i'] = self.clk_sel
        self.cpu_params['o_pll_48_o'] = self.pll_48_o
        self.padresources = io()
        self.pad_cm = ConstraintManager(self.padresources, [])
        self.cpupads = {}
        iopads = {}
        litexmap = {}
        subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
                  'pwm', 'sd0', 'sdr'}
        for periph in subset:
            origperiph = periph
            num = None
            if periph[-1].isdigit():
                periph, num = periph[:-1], int(periph[-1])
            print ("periph request", periph, num)
            if periph == 'mspi':
                if num == 0:
                    periph, num = 'spimaster', None
                else:
                    periph, num = 'spisdcard', None
            elif periph == 'sdr':
                periph = 'sdram'
            elif periph == 'mtwi':
                periph = 'i2c'
            elif periph == 'sd':
                periph, num = 'sdcard', None
            litexmap[origperiph] = (periph, num)
            self.cpupads[origperiph] = platform.request(periph, num)
            iopads[origperiph] = self.pad_cm.request(periph, num)
            if periph == 'sdram':
                # special-case sdram clock
                ck = platform.request("sdram_clock")
                self.cpupads['sdram_clock'] = ck
                ck = self.pad_cm.request("sdram_clock")
                iopads['sdram_clock'] = ck

        pinset = get_pinspecs(subset=subset)
        p = Pins(pinset)
        for pin in list(p):
            make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)

        # add verilog sources
        self.add_sources(platform)


Return to bug 519

Lines 9-23 from soc.config.pinouts import get_pinspecs Link Here

(-)a/src/soc/litex/florent/libresoc/core.py (-107 / +106 lines)
9	from soc.debug.jtag import Pins	9	from soc.debug.jtag import Pins
10	from c4m.nmigen.jtag.tap import IOType	10	from c4m.nmigen.jtag.tap import IOType
11		11
12	from libresoc.ls180 import io	12	from ls180 import io
13	from litex.build.generic_platform import ConstraintManager	13	from litex.build.generic_platform import ConstraintManager
14		14
15
16	CPU_VARIANTS = ["standard", "standard32", "standardjtag",
17	"standardjtagtestgpio", "ls180",
18	"standardjtagnoirq"]
19
20
21	def make_wb_bus(prefix, obj, simple=False):	15	def make_wb_bus(prefix, obj, simple=False):
22	res = {}	16	res = {}
23	outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']	17	outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
Lines 48-54 def get_field(rec, name): Link Here
48	if f.endswith(name):	42	if f.endswith(name):
49	return getattr(rec, f)	43	return getattr(rec, f)
50		44
51
52	def make_jtag_ioconn(res, pin, cpupads, iopads):	45	def make_jtag_ioconn(res, pin, cpupads, iopads):
53	(fn, pin, iotype, pin_name, scan_idx) = pin	46	(fn, pin, iotype, pin_name, scan_idx) = pin
54	#serial_tx__core__o, serial_rx__pad__i,	47	#serial_tx__core__o, serial_rx__pad__i,
Lines 119-125 def make_jtag_ioconn(res, pin, cpupads, iopads): Link Here
119	class LibreSoC(CPU):	112	class LibreSoC(CPU):
120	name = "libre_soc"	113	name = "libre_soc"
121	human_name = "Libre-SoC"	114	human_name = "Libre-SoC"
122	variants = CPU_VARIANTS
123	endianness = "little"	115	endianness = "little"
124	gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")	116	gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu")
125	linker_output_format = "elf64-powerpcle"	117	linker_output_format = "elf64-powerpcle"
Lines 146-194 class LibreSoC(CPU): Link Here
146	flags += "-D__microwatt__ "	138	flags += "-D__microwatt__ "
147	return flags	139	return flags
148		140
149	def __init__(self, platform, variant="standard"):	141	def __init__(self, platform, dmi=True, add_sources=True):
150	self.platform = platform	142	self.platform = platform
151	self.variant = variant
152	self.reset = Signal()	143	self.reset = Signal()
153	irq_en = "noirq" not in variant	144	self.interrupt = Signal(16)
154		145
155	if irq_en:	146	self.data_width = 64
156	self.interrupt = Signal(16)	147	self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
157
158	if variant == "standard32":
159	self.data_width = 32
160	self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
161	else:
162	self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
163	self.data_width = 64
164	self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)	148	self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
165		149
166	self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)	150	self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
167	self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)	151	self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
168		152
169	jtag_en = ('jtag' in variant) or variant == 'ls180'
170
171	if "testgpio" in variant:
172	self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
173	if jtag_en:
174	self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
175		153
176	self.periph_buses = [ibus, dbus]	154	self.periph_buses = [ibus, dbus]
177	self.memory_buses = []	155	self.memory_buses = []
178		156
179	if jtag_en:
180	self.periph_buses.append(jtag_wb)
181	self.jtag_tck = Signal(1)
182	self.jtag_tms = Signal(1)
183	self.jtag_tdi = Signal(1)
184	self.jtag_tdo = Signal(1)
185	else:
186	self.dmi_addr = Signal(4)
187	self.dmi_din = Signal(64)
188	self.dmi_dout = Signal(64)
189	self.dmi_wr = Signal(1)
190	self.dmi_ack = Signal(1)
191	self.dmi_req = Signal(1)
192		157
193	# # #	158	# # #
194		159
Lines 207-225 class LibreSoC(CPU): Link Here
207		172
208	)	173	)
209		174
210	if irq_en:	175	# interrupts
211	# interrupts	176	self.cpu_params['i_int_level_i'] = self.interrupt
212	self.cpu_params['i_int_level_i'] = self.interrupt
213		177
214	if jtag_en:	178	if dmi:
215	self.cpu_params.update(dict(	179	self.dmi_addr = Signal(4)
216	# JTAG Debug bus	180	self.dmi_din = Signal(64)
217	o_TAP_bus__tdo = self.jtag_tdo,	181	self.dmi_dout = Signal(64)
218	i_TAP_bus__tdi = self.jtag_tdi,	182	self.dmi_wr = Signal(1)
219	i_TAP_bus__tms = self.jtag_tms,	183	self.dmi_ack = Signal(1)
220	i_TAP_bus__tck = self.jtag_tck,	184	self.dmi_req = Signal(1)
221	))
222	else:
223	self.cpu_params.update(dict(	185	self.cpu_params.update(dict(
224	# DMI Debug bus	186	# DMI Debug bus
225	i_dmi_addr_i = self.dmi_addr,	187	i_dmi_addr_i = self.dmi_addr,
Lines 230-296 class LibreSoC(CPU): Link Here
230	o_dmi_ack_o = self.dmi_ack,	192	o_dmi_ack_o = self.dmi_ack,
231	))	193	))
232		194
233	# add clock select, pll output
234	if variant == "ls180":
235	self.pll_48_o = Signal()
236	self.clk_sel = Signal(3)
237	self.cpu_params['i_clk_sel_i'] = self.clk_sel
238	self.cpu_params['o_pll_48_o'] = self.pll_48_o
239
240	# add wishbone buses to cpu params	195	# add wishbone buses to cpu params
241	self.cpu_params.update(make_wb_bus("ibus", ibus))	196	self.cpu_params.update(make_wb_bus("ibus", ibus))
242	self.cpu_params.update(make_wb_bus("dbus", dbus))	197	self.cpu_params.update(make_wb_bus("dbus", dbus))
243	self.cpu_params.update(make_wb_slave("ics_wb", ics))	198	self.cpu_params.update(make_wb_slave("ics_wb", ics))
244	self.cpu_params.update(make_wb_slave("icp_wb", icp))	199	self.cpu_params.update(make_wb_slave("icp_wb", icp))
245	if "testgpio" in variant:
246	self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
247	if jtag_en:
248	self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
249
250	if variant == 'ls180':
251	# urr yuk. have to expose iopads / pins from core to litex
252	# then back again. cut _some_ of that out by connecting
253	self.padresources = io()
254	self.pad_cm = ConstraintManager(self.padresources, [])
255	self.cpupads = {}
256	iopads = {}
257	litexmap = {}
258	subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
259	'pwm', 'sd0', 'sdr'}
260	for periph in subset:
261	origperiph = periph
262	num = None
263	if periph[-1].isdigit():
264	periph, num = periph[:-1], int(periph[-1])
265	print ("periph request", periph, num)
266	if periph == 'mspi':
267	if num == 0:
268	periph, num = 'spimaster', None
269	else:
270	periph, num = 'spisdcard', None
271	elif periph == 'sdr':
272	periph = 'sdram'
273	elif periph == 'mtwi':
274	periph = 'i2c'
275	elif periph == 'sd':
276	periph, num = 'sdcard', None
277	litexmap[origperiph] = (periph, num)
278	self.cpupads[origperiph] = platform.request(periph, num)
279	iopads[origperiph] = self.pad_cm.request(periph, num)
280	if periph == 'sdram':
281	# special-case sdram clock
282	ck = platform.request("sdram_clock")
283	self.cpupads['sdram_clock'] = ck
284	ck = self.pad_cm.request("sdram_clock")
285	iopads['sdram_clock'] = ck
286
287	pinset = get_pinspecs(subset=subset)
288	p = Pins(pinset)
289	for pin in list(p):
290	make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
291		200
292	# add verilog sources	201	if add_sources:
293	self.add_sources(platform)	202	# add verilog sources
		203	self.add_sources(platform)
294		204
295	def set_reset_address(self, reset_address):	205	def set_reset_address(self, reset_address):
296	assert not hasattr(self, "reset_address")	206	assert not hasattr(self, "reset_address")
Lines 305-307 class LibreSoC(CPU): Link Here
305	def do_finalize(self):	215	def do_finalize(self):
306	self.specials += Instance("test_issuer", **self.cpu_params)	216	self.specials += Instance("test_issuer", **self.cpu_params)
307		217
		218	class LS32(LibreSoC):
		219	def __init__(self):
		220	super().__init__(dbus=wb.Interface(data_width=64, adr_width=29))
		221	self.data_width = 32
		222	self.dbus = dbus = wb.Interface(data_width=self.data_width,
		223	adr_width=30)
		224	self.cpu_params.update(make_wb_bus("dbus", dbus))
		225	self.periph_buses[1] = dbus
		226
		227	class LSJTAG(LibreSoC):
		228	def __init__(self):
		229	super().__init__(dmi=False)
		230	self.jtag_tck = Signal(1)
		231	self.jtag_tms = Signal(1)
		232	self.jtag_tdi = Signal(1)
		233	self.jtag_tdo = Signal(1)
		234	self.cpu_params.update(dict(
		235	# JTAG Debug bus
		236	o_TAP_bus__tdo = self.jtag_tdo,
		237	i_TAP_bus__tdi = self.jtag_tdi,
		238	i_TAP_bus__tms = self.jtag_tms,
		239	i_TAP_bus__tck = self.jtag_tck,
		240	))
		241	self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
		242	self.periph_buses.append(jtag_wb)
		243	self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
		244
		245
		246	class LSNoIRQ(LSJTAG):
		247	def __init__(self):
		248	super().__init__()
		249	del(self.interrupt)
		250	self.cpu_params.pop('i_int_level_i')
		251
		252	class LSGPIO(LSNoIRQ):
		253	def __init__(self):
		254	super().__init__()
		255	self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
		256	self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
		257
		258	class LS180(LSJTAG):
		259	def __init__(self):
		260	super().__init__(add_sources=False)
		261	self.pll_48_o = Signal()
		262	self.clk_sel = Signal(3)
		263	self.cpu_params['i_clk_sel_i'] = self.clk_sel
		264	self.cpu_params['o_pll_48_o'] = self.pll_48_o
		265	self.padresources = io()
		266	self.pad_cm = ConstraintManager(self.padresources, [])
		267	self.cpupads = {}
		268	iopads = {}
		269	litexmap = {}
		270	subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
		271	'pwm', 'sd0', 'sdr'}
		272	for periph in subset:
		273	origperiph = periph
		274	num = None
		275	if periph[-1].isdigit():
		276	periph, num = periph[:-1], int(periph[-1])
		277	print ("periph request", periph, num)
		278	if periph == 'mspi':
		279	if num == 0:
		280	periph, num = 'spimaster', None
		281	else:
282	periph, num = 'spisdcard', None
283	elif periph == 'sdr':
284	periph = 'sdram'
285	elif periph == 'mtwi':
286	periph = 'i2c'
287	elif periph == 'sd':
288	periph, num = 'sdcard', None
289	litexmap[origperiph] = (periph, num)
290	self.cpupads[origperiph] = platform.request(periph, num)
291	iopads[origperiph] = self.pad_cm.request(periph, num)
292	if periph == 'sdram':
293	# special-case sdram clock
294	ck = platform.request("sdram_clock")
295	self.cpupads['sdram_clock'] = ck
296	ck = self.pad_cm.request("sdram_clock")
297	iopads['sdram_clock'] = ck
298
299	pinset = get_pinspecs(subset=subset)
300	p = Pins(pinset)
301	for pin in list(p):
302	make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)
303
304	# add verilog sources
305	self.add_sources(platform)
306