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Lines 643-648
extract_nsi34 (uint64_t insn,
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| 643 |
return -value; |
643 |
return -value; |
| 644 |
} |
644 |
} |
| 645 |
|
645 |
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|
646 |
/* The non-contiguous 24-bits of operands in a svp64 prefix. */ |
| 647 |
static uint64_t |
| 648 |
insert_svp64imm24 (uint64_t insn, |
| 649 |
int64_t value, |
| 650 |
ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| 651 |
const char **errmsg ATTRIBUTE_UNUSED) |
| 652 |
{ |
| 653 |
if (value & ~(int64_t)0xffffff) |
| 654 |
*errmsg = _("illegal immediate value"); |
| 655 |
|
| 656 |
return insn |
| 657 |
| ((value & 0x800000) << 2) |
| 658 |
| ((value & 0x400000) << 1) |
| 659 |
| (value & 0x3fffff); |
| 660 |
} |
| 661 |
|
| 662 |
static int64_t |
| 663 |
extract_svp64imm24 (uint64_t insn, |
| 664 |
ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| 665 |
int *invalid ATTRIBUTE_UNUSED) |
| 666 |
{ |
| 667 |
return 0 |
| 668 |
| ((insn & 0x2000000) >> 2) |
| 669 |
| ((insn & 0x0800000) >> 1) |
| 670 |
| ((insn & 0x03fffff)); |
| 671 |
} |
| 672 |
|
| 646 |
/* The split IMM32 field in a vector splat insn. */ |
673 |
/* The split IMM32 field in a vector splat insn. */ |
| 647 |
|
674 |
|
| 648 |
static uint64_t |
675 |
static uint64_t |
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Lines 2451-2458
const struct powerpc_operand powerpc_operands[] =
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| 2451 |
{ UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34, |
2478 |
{ UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34, |
| 2452 |
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
2479 |
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
| 2453 |
|
2480 |
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|
2481 |
/* The 24 non-contiguous bits that encode the operands for an SVP64 |
| 2482 |
prefix. */ |
| 2483 |
#define SVP64IMM24 NSI34 + 1 |
| 2484 |
/*0x2bfffff is the actual mask, but some pieces of the assembler |
| 2485 |
require a contiguous bit pattern. */ |
| 2486 |
{ 0x3ffffff, PPC_OPSHIFT_INV, insert_svp64imm24, extract_svp64imm24, 0}, |
| 2487 |
|
| 2454 |
/* The IMM32 field in a vector splat immediate prefix instruction. */ |
2488 |
/* The IMM32 field in a vector splat immediate prefix instruction. */ |
| 2455 |
#define IMM32 NSI34 + 1 |
2489 |
#define IMM32 SVP64IMM24 + 1 |
| 2456 |
{ 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0}, |
2490 |
{ 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0}, |
| 2457 |
|
2491 |
|
| 2458 |
/* The UIM field in a vector permute extended prefix instruction. */ |
2492 |
/* The UIM field in a vector permute extended prefix instruction. */ |
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Lines 4215-4221
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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| 4215 |
for the 3 operand dcbt and dcbtst instructions. */ |
4249 |
for the 3 operand dcbt and dcbtst instructions. */ |
| 4216 |
#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ |
4250 |
#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ |
| 4217 |
| PPC_OPCODE_A2) |
4251 |
| PPC_OPCODE_A2) |
| 4218 |
|
4252 |
#define LIBRESOC PPC /* FIXME */ |
| 4219 |
|
4253 |
|
| 4220 |
|
4254 |
|
| 4221 |
/* The opcode table. |
4255 |
/* The opcode table. |
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Lines 4242-4247
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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| 4242 |
|
4276 |
|
| 4243 |
const struct powerpc_opcode powerpc_opcodes[] = { |
4277 |
const struct powerpc_opcode powerpc_opcodes[] = { |
| 4244 |
{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, |
4278 |
{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, |
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|
4279 |
|
| 4280 |
{"svp64", 0x05400000, 0xfd400000, LIBRESOC, PPCVLE, {SVP64IMM24}}, |
| 4281 |
|
| 4245 |
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
4282 |
{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
| 4246 |
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
4283 |
{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
| 4247 |
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |
4284 |
{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}}, |