Attachment #125 for bug #600

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Lines 706-712 class ISACaller: Link Here

(-)a/src/soc/decoder/isa/caller.py (-1 / +1 lines)
706	print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))	706	print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
707	print (" svstate.vl", self.svstate.vl.asint(msb0=True))	707	print (" svstate.vl", self.svstate.vl.asint(msb0=True))
708	print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))	708	print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
709	sv_rm = pfx.rm.asint()	709	sv_rm = pfx.rm.asint(msb0=True)
710	ins = self.imem.ld(pc+4, 4, False, True)	710	ins = self.imem.ld(pc+4, 4, False, True)
711	print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))	711	print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
712	yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix	712	yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix




            # 2-bit index selection mode
            with m.Case(SVEtype.EXTRA2):
                with m.Switch(self.idx):
                    with m.Case(SVEXTRA.Idx0): # 1st 2 bits [0:1]
                        comb += spec[1:3].eq(self.extra[8-1:9])
                    with m.Case(SVEXTRA.Idx1): # 2nd 2 bits [2:3]
                        comb += spec[1:3].eq(self.extra[8-3:8-1])
                    with m.Case(SVEXTRA.Idx2): # 3rd 2 bits [4:5]
                        comb += spec[1:3].eq(self.extra[8-5:8-3])
                    with m.Case(SVEXTRA.Idx3): # 4th 2 bits [6:7]
                        comb += spec[1:3].eq(self.extra[8-7:8-5])
            # 3-bit index selection mode
            with m.Case(SVEtype.EXTRA3):
                with m.Switch(self.idx):
                    with m.Case(SVEXTRA.Idx0): # 1st 3 bits [0:2]
                        comb += spec.eq(self.extra[8-2:9])
                    with m.Case(SVEXTRA.Idx1): # 2nd 3 bits [3:5]
                        comb += spec.eq(self.extra[8-5:8-2])
                    with m.Case(SVEXTRA.Idx2): # 3rd 3 bits [6:8]
                        comb += spec.eq(self.extra[8-8:8-5])
                    # cannot fit more than 9 bits so there is no 4th thing

        return m

        l = []
        for idx in rmfields:
            l.append(self.opcode_in[31-idx])
        # in nMigen, Cat begins at the LSB and proceeds upwards
        l.reverse()  # put the LSB at the start of the list
        with m.If(self.is_svp64_mode):
            comb += self.svp64_rm.eq(Cat(*l))


Lines 18-34 https://libre-soc.org/openpower/sv/svp64/ Link Here

(-)a/src/soc/sv/svp64.py (-7 / +8 lines)
18		18
19	from nmigen import Record	19	from nmigen import Record
20		20
		21
		22	# in nMigen, Record begins at the LSB and fills upwards
21	class SVP64Rec(Record):	23	class SVP64Rec(Record):
22	def __init__(self, name=None):	24	def __init__(self, name=None):
23	Record.__init__(self, layout=[("mmode" , 1),	25	Record.__init__(self, layout=[("mode" , 5),
24	("mask" , 3),
25	("elwidth" , 2),
26	("ewsrc" , 2),
27	("subvl" , 2),
28	("extra" , 9),	26	("extra" , 9),
29	("mode" , 5)], name=name)	27	("subvl" , 2),
		28	("ewsrc" , 2),
		29	("elwidth" , 2),
		30	("mask" , 3),
		31	("mmode" , 1)], name=name)
30		32
31	def ports(self):	33	def ports(self):
32	return [self.mmode, self.mask, self.elwidth, self.ewsrc,	34	return [self.mmode, self.mask, self.elwidth, self.ewsrc,
33	self.extra, self.mode]	35	self.extra, self.mode]
34




from nmigen import Signal


# In nMigen, Record order is from LSB to MSB
class SVSTATERec(RecordObject):
    def __init__(self, name=None):
        super().__init__(name=name)
        self.maxvl = Signal(7)
        self.vl = Signal(7)
        self.srcstep = Signal(7)
        self.dststep = Signal(7)
        self.subvl = Signal(2)
        self.svstep = Signal(2)
        self.subvl = Signal(2)
        self.dststep = Signal(7)
        self.srcstep = Signal(7)
        self.vl = Signal(7)
        self.maxvl = Signal(7)




                if idx is None: continue
                # start at bit 10, work up 2/3 times EXTRA idx
                offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
                svp64_rm |= sv_extra << (32-offs-(10+idx*offs))

            # parts of svp64_rm
            mmode = 0  # bit 0

            # whewww.... modes all done :)
            # now put into svp64_rm
            mode |= sv_mode
            svp64_rm |= (mode << 23-23) # mode: bits 19-23

            # put in predicate masks into svp64_rm
            if ptype == '2P':
                svp64_rm |= (smask << 23-18) # source pred: bits 16-18
            svp64_rm |= (mmode << 23-0)           # mask mode: bit 0
            svp64_rm |= (pmask << 23-3)      # 1-pred: bits 1-3

            # and subvl
            svp64_rm += (subvl << 23-9)      # subvl: bits 8-9

            # put in elwidths
            svp64_rm += (srcwid << 23-7)      # srcwid: bits 6-7
            svp64_rm += (destwid << 23-5)     # destwid: bits 4-5

            # nice debug printout. (and now for something completely different)
            # https://youtu.be/u0WOIwlXE9g?t=146

            svp64_prefix |= 0x1 << (31-9) # SVP64 marker 2
            rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
            for i, x in enumerate(rmfields):
                svp64_prefix |= ((svp64_rm>>(31-i))&0b1) << (31-x)

            # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
            yield ".long 0x%x" % svp64_prefix

Return to bug 600

Lines 104-126 class SVP64ExtraSpec(Elaboratable): Link Here

(-)a/src/soc/decoder/power_decoder2.py (-14 / +16 lines)
104	# 2-bit index selection mode	104	# 2-bit index selection mode
105	with m.Case(SVEtype.EXTRA2):	105	with m.Case(SVEtype.EXTRA2):
106	with m.Switch(self.idx):	106	with m.Switch(self.idx):
107	with m.Case(SVEXTRA.Idx0): # 1st 2 bits	107	with m.Case(SVEXTRA.Idx0): # 1st 2 bits [0:1]
108	comb += spec[1:3].eq(self.extra[0:2])	108	comb += spec[1:3].eq(self.extra[8-1:9])
109	with m.Case(SVEXTRA.Idx1): # 2nd 2 bits	109	with m.Case(SVEXTRA.Idx1): # 2nd 2 bits [2:3]
110	comb += spec[1:3].eq(self.extra[2:4])	110	comb += spec[1:3].eq(self.extra[8-3:8-1])
111	with m.Case(SVEXTRA.Idx2): # 3rd 2 bits	111	with m.Case(SVEXTRA.Idx2): # 3rd 2 bits [4:5]
112	comb += spec[1:3].eq(self.extra[4:6])	112	comb += spec[1:3].eq(self.extra[8-5:8-3])
113	with m.Case(SVEXTRA.Idx3): # 4th 2 bits	113	with m.Case(SVEXTRA.Idx3): # 4th 2 bits [6:7]
114	comb += spec[1:3].eq(self.extra[6:8])	114	comb += spec[1:3].eq(self.extra[8-7:8-5])
115	# 3-bit index selection mode	115	# 3-bit index selection mode
116	with m.Case(SVEtype.EXTRA3):	116	with m.Case(SVEtype.EXTRA3):
117	with m.Switch(self.idx):	117	with m.Switch(self.idx):
118	with m.Case(SVEXTRA.Idx0): # 1st 3 bits	118	with m.Case(SVEXTRA.Idx0): # 1st 3 bits [0:2]
119	comb += spec.eq(self.extra[0:3])	119	comb += spec.eq(self.extra[8-2:9])
120	with m.Case(SVEXTRA.Idx1): # 2nd 3 bits	120	with m.Case(SVEXTRA.Idx1): # 2nd 3 bits [3:5]
121	comb += spec.eq(self.extra[3:6])	121	comb += spec.eq(self.extra[8-5:8-2])
122	with m.Case(SVEXTRA.Idx2): # 3rd 3 bits	122	with m.Case(SVEXTRA.Idx2): # 3rd 3 bits [6:8]
123	comb += spec.eq(self.extra[6:9])	123	comb += spec.eq(self.extra[8-8:8-5])
124	# cannot fit more than 9 bits so there is no 4th thing	124	# cannot fit more than 9 bits so there is no 4th thing
125		125
126	return m	126	return m
Lines 1327-1332 class SVP64PrefixDecoder(Elaboratable): Link Here
1327	l = []	1327	l = []
1328	for idx in rmfields:	1328	for idx in rmfields:
1329	l.append(self.opcode_in[31-idx])	1329	l.append(self.opcode_in[31-idx])
		1330	# in nMigen, Cat begins at the LSB and proceeds upwards
		1331	l.reverse() # put the LSB at the start of the list
1330	with m.If(self.is_svp64_mode):	1332	with m.If(self.is_svp64_mode):
1331	comb += self.svp64_rm.eq(Cat(*l))	1333	comb += self.svp64_rm.eq(Cat(*l))
1332		1334

Lines 336-342 class SVP64Asm: Link Here

(-)a/src/soc/sv/trans/svp64.py (-9 / +9 lines)
336	if idx is None: continue	336	if idx is None: continue
337	# start at bit 10, work up 2/3 times EXTRA idx	337	# start at bit 10, work up 2/3 times EXTRA idx
338	offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits	338	offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
339	svp64_rm \|= sv_extra << (10+idx*offs)	339	svp64_rm \|= sv_extra << (32-offs-(10+idx*offs))
340		340
341	# parts of svp64_rm	341	# parts of svp64_rm
342	mmode = 0 # bit 0	342	mmode = 0 # bit 0
Lines 503-522 class SVP64Asm: Link Here
503	# whewww.... modes all done :)	503	# whewww.... modes all done :)
504	# now put into svp64_rm	504	# now put into svp64_rm
505	mode \|= sv_mode	505	mode \|= sv_mode
506	svp64_rm \|= (mode << 19) # mode: bits 19-23	506	svp64_rm \|= (mode << 23-23) # mode: bits 19-23
507		507
508	# put in predicate masks into svp64_rm	508	# put in predicate masks into svp64_rm
509	if ptype == '2P':	509	if ptype == '2P':
510	svp64_rm \|= (smask << 16) # source pred: bits 16-18	510	svp64_rm \|= (smask << 23-18) # source pred: bits 16-18
511	svp64_rm \|= (mmode) # mask mode: bit 0	511	svp64_rm \|= (mmode << 23-0) # mask mode: bit 0
512	svp64_rm \|= (pmask << 1) # 1-pred: bits 1-3	512	svp64_rm \|= (pmask << 23-3) # 1-pred: bits 1-3
513		513
514	# and subvl	514	# and subvl
515	svp64_rm += (subvl << 8) # subvl: bits 8-9	515	svp64_rm += (subvl << 23-9) # subvl: bits 8-9
516		516
517	# put in elwidths	517	# put in elwidths
518	svp64_rm += (srcwid << 6) # srcwid: bits 6-7	518	svp64_rm += (srcwid << 23-7) # srcwid: bits 6-7
519	svp64_rm += (destwid << 4) # destwid: bits 4-5	519	svp64_rm += (destwid << 23-5) # destwid: bits 4-5
520		520
521	# nice debug printout. (and now for something completely different)	521	# nice debug printout. (and now for something completely different)
522	# https://youtu.be/u0WOIwlXE9g?t=146	522	# https://youtu.be/u0WOIwlXE9g?t=146
Lines 544-550 class SVP64Asm: Link Here
544	svp64_prefix \|= 0x1 << (31-9) # SVP64 marker 2	544	svp64_prefix \|= 0x1 << (31-9) # SVP64 marker 2
545	rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM	545	rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM
546	for i, x in enumerate(rmfields):	546	for i, x in enumerate(rmfields):
547	svp64_prefix \|= ((svp64_rm>>i)&0b1) << (31-x)	547	svp64_prefix \|= ((svp64_rm>>(31-i))&0b1) << (31-x)
548		548
549	# fiinally yield the svp64 prefix and the thingy. v3.0b opcode	549	# fiinally yield the svp64 prefix and the thingy. v3.0b opcode
550	yield ".long 0x%x" % svp64_prefix	550	yield ".long 0x%x" % svp64_prefix

Lines 19-31 from nmutil.iocontrol import RecordObject Link Here

(-)a/src/soc/sv/svstate.py (-6 / +6 lines)
19	from nmigen import Signal	19	from nmigen import Signal
20		20
21		21
		22	# In nMigen, Record order is from LSB to MSB
22	class SVSTATERec(RecordObject):	23	class SVSTATERec(RecordObject):
23	def __init__(self, name=None):	24	def __init__(self, name=None):
24	super().__init__(name=name)	25	super().__init__(name=name)
25	self.maxvl = Signal(7)
26	self.vl = Signal(7)
27	self.srcstep = Signal(7)
28	self.dststep = Signal(7)
29	self.subvl = Signal(2)
30	self.svstep = Signal(2)	26	self.svstep = Signal(2)
31		27	self.subvl = Signal(2)
		28	self.dststep = Signal(7)
		29	self.srcstep = Signal(7)
		30	self.vl = Signal(7)
		31	self.maxvl = Signal(7)