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(-)a/openpower/sv/svp64.mdwn (-3 / +3 lines)
Lines 485-494 A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/append Link Here
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        spec = EXTRA3
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        spec = EXTRA3
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    else:
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    else:
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        spec = EXTRA2 << 1 # same as EXTRA3, shifted
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        spec = EXTRA2 << 1 # same as EXTRA3, shifted
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    if spec[2]: # vector
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    if spec[0]: # vector
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         return (RA << 2) | spec[0:1]
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         return (RA << 2) | spec[1:2]
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    else:         # scalar
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    else:         # scalar
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         return (spec[0:1] << 5) | RA
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         return (spec[1:2] << 5) | RA
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Future versions may extend to 256 by shifting Vector numbering up.
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Future versions may extend to 256 by shifting Vector numbering up.
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Scalar will not be altered.
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Scalar will not be altered.
(-)a/openpower/sv/svp64/appendix.mdwn (-12 / +11 lines)
Lines 442-449 or v3.1B specification*). However with some care and consideration Link Here
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the exact same mapping used for INT and FP regfiles may be applied,
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the exact same mapping used for INT and FP regfiles may be applied,
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just to the upper bits, as explained below.
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just to the upper bits, as explained below.
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In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits.  The top 3 bits (2:4)
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In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits.  The top 3 bits (0:2)
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select one of the 8 CRs; the bottom 2 bits (0:1) select one of 4 bits
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select one of the 8 CRs; the bottom 2 bits (3:4) select one of 4 bits
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*in* that CR.  The numbering was determined (after 4 months of
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*in* that CR.  The numbering was determined (after 4 months of
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analysis and research) to be as follows:
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analysis and research) to be as follows:
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Lines 454-484 analysis and research) to be as follows: Link Here
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    CR_bit = (CR_reg & (1<<bit_index)) != 0
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    CR_bit = (CR_reg & (1<<bit_index)) != 0
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When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
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When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
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applies, **not** the CR\_bit portion (bits 0:1):
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applies, **not** the CR\_bit portion (bits 3:4):
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    if extra3_mode:
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    if extra3_mode:
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        spec = EXTRA3
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        spec = EXTRA3
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    else:
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    else:
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        spec = EXTRA2<<1 | 0b0
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        spec = EXTRA2<<1 | 0b0
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    if spec[2]:
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    if spec[0]:
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       # vector constructs "BA[2:4] spec[0:1] 00 BA[0:1]"
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       # vector constructs "BA[0:2] spec[1:2] 00 BA[3:4]"
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       return ((BA >> 2)<<6) | # hi 3 bits shifted up
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       return ((BA >> 2)<<6) | # hi 3 bits shifted up
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              (spec[0:1]<<4) | # to make room for these
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              (spec[1:2]<<4) | # to make room for these
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              (BA & 0b11)      # CR_bit on the end
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              (BA & 0b11)      # CR_bit on the end
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    else:
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    else:
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       # scalar constructs "00 spec[0:1] BA[0:4]"
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       # scalar constructs "00 spec[1:2] BA[0:4]"
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       return (spec[0:1] << 5) | BA
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       return (spec[1:2] << 5) | BA
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Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
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Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
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algorithm to determin CR\_reg is modified to as follows:
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algorithm to determin CR\_reg is modified to as follows:
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    CR_index = 7-(BA>>2)      # top 3 bits but BE
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    CR_index = 7-(BA>>2)      # top 3 bits but BE
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    if spec[2]:
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    if spec[0]:
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        # vector mode, 0-124 increments of 4
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        # vector mode, 0-124 increments of 4
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        CR_index = (CR_index<<4) | (spec[0:1] << 2)
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        CR_index = (CR_index<<4) | (spec[1:2] << 2)
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    else:
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    else:
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        # scalar mode, 0-32 increments of 1
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        # scalar mode, 0-32 increments of 1
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        CR_index = (spec[0:1]<<3) | CR_index
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        CR_index = (spec[1:2]<<3) | CR_index
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    # same as for v3.0/v3.1 from this point onwards
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    # same as for v3.0/v3.1 from this point onwards
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    bit_index = 3-(BA & 0b11) # low 2 bits but BE
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    bit_index = 3-(BA & 0b11) # low 2 bits but BE
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    CR_reg = CR{CR_index}     # get the CR
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    CR_reg = CR{CR_index}     # get the CR
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