Attachment #132 for bug #635

View | Details | Raw Unified | Return to bug 635
Collapse All | Expand All

Line 1 Link Here

(-)a/libreriscv (-1 / +1 lines)
1	Subproject commit 365cec3d5377e618199acfdf7f26545238aacdca	1	Subproject commit 365cec3d5377e618199acfdf7f26545238aacdca-dirty

Line 1 Link Here

(-)a/nmigen-type-annotations (-1 / +1 lines)
1	Subproject commit 227f39952a4529cea7f5da76c361bf6b650adff3	1	Subproject commit 227f39952a4529cea7f5da76c361bf6b650adff3-dirty

Line 1 Link Here

(-)a/src/soc/litex/florent (-1 / +1 lines)
1	Subproject commit 3f163ae167c3d17b3e8cc2a050a60ab20a6bdba2	1	Subproject commit 3f163ae167c3d17b3e8cc2a050a60ab20a6bdba2-dirty

Lines 106-112 def setup_regs(pdecode2, core, test): Link Here

(-)a/src/soc/simple/test/test_core.py (-1 / +5 lines)
106	(i, sprname, val))	106	(i, sprname, val))
107	yield sregs.memory._array[i].eq(val)	107	yield sregs.memory._array[i].eq(val)
108	else:	108	else:
109	yield fregs.regs[fast].reg.eq(val)	109	val = test.regs[i]
		110	if intregs.unary:
		111	yield fregs.regs[i].reg.eq(val)
		112	else:
		113	yield fregs.memory._array[i].eq(val)
110	print("setting fast reg %d (%s) to %x" %	114	print("setting fast reg %d (%s) to %x" %
111	(fast, sprname, val))	115	(fast, sprname, val))
112		116




from soc.simple.test.test_runner import TestRunner

# test with ALU data and Logical data
#from soc.fu.alu.test.test_pipe_caller import ALUTestCase
#from soc.fu.div.test.test_pipe_caller import DivTestCases
#from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
#from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
#from soc.fu.cr.test.test_pipe_caller import CRTestCase
from soc.fu.branch.test.test_pipe_caller import BranchTestCase
# from soc.fu.spr.test.test_pipe_caller import SPRTestCase
#from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
#from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
# from soc.simulator.test_helloworld_sim import HelloTestCases



    unittest.main(exit=False)
    suite = unittest.TestSuite()
    # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))
    #suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
    # suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))
    #suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))
    #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
    #suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
    #suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
    #suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
    #suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
    suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64))
    # suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))

    runner = unittest.TextTestRunner()





                print(test.name)
                program = test.program
                with self.subTest(test.name):
                    print("regs", test.regs)
                    print("sprs", test.sprs)
                    print("cr", test.cr)
                    print("mem", test.mem)
                    print("msr", test.msr)
                    print("assem", program.assembly)
                    gen = list(program.generate_instructions())
                    insncode = program.assembly.splitlines()
                    instructions = list(zip(gen, insncode))

                    # set up the Simulator (which must track TestIssuer exactly)
                    sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
                              test.msr,
                              initial_insns=gen, respect_pc=True,
                              disassembly=insncode,
                              bigendian=bigendian,
                              initial_svstate=test.svstate)

                    # establish the TestIssuer context (mem, regs etc)

                    pc = 0  # start address
                    counter = 0  # test to pause/start

                    yield from setup_i_memory(imem, pc, instructions)
                    yield from setup_test_memory(l0, sim)
                    yield from setup_regs(pdecode2, core, test)

                    # set PC and SVSTATE
                    yield pc_i.eq(pc)
                    yield issuer.pc_i.ok.eq(1)

                    initial_svstate = test.svstate
                    if isinstance(initial_svstate, int):
                        initial_svstate = SVP64State(initial_svstate)
                    yield svstate_i.eq(initial_svstate.spr.value)
                    yield issuer.svstate_i.ok.eq(1)
                    yield

                print("instructions", instructions)

                # run the loop of the instructions on the current test
                index = sim.pc.CIA.value//4
                while index < len(instructions):
                    ins, code = instructions[index]

                    print("instruction: 0x{:X}".format(ins & 0xffffffff))
                    print(index, code)

                    if counter == 0:
                        # start the core
                        yield
                        yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
                        yield issuer.pc_i.ok.eq(0)  # no change PC after this
                        yield issuer.svstate_i.ok.eq(0) # ditto
                        yield
                        yield

                    print("instructions", instructions)

                    # run the loop of the instructions on the current test
                    # wait for insn_done high
                    while not (yield issuer.insn_done):
                        yield
                    # wait for insn_done low
                    while (yield issuer.insn_done):
                        yield

                    # set up simulated instruction (in simdec2)
                    try:
                        yield from sim.setup_one()
                    except KeyError:  # indicates instruction not in imem: stop
                        break
                    yield Settle()

                    # call simulated operation
                    print("sim", code)
                    yield from sim.execute_one()
                    yield Settle()
                    index = sim.pc.CIA.value//4
                    while index < len(instructions):
                        ins, code = instructions[index]

                        print("instruction: 0x{:X}".format(ins & 0xffffffff))
                        print(index, code)

                        if counter == 0:
                            # start the core
                            yield
                            yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
                            yield issuer.pc_i.ok.eq(0)  # no change PC after this
                            yield issuer.svstate_i.ok.eq(0) # ditto
                            yield
                            yield

                        counter = counter + 1

                        # wait until executed
                        # wait for insn_done high
                        while not (yield issuer.insn_done):
                            yield
                        # wait for insn_done low
                        while (yield issuer.insn_done):
                            yield

                        # set up simulated instruction (in simdec2)
                        try:
                            yield from sim.setup_one()
                        except KeyError:  # indicates instruction not in imem: stop
                            break
                        yield Settle()

                        # call simulated operation
                        print("sim", code)
                        yield from sim.execute_one()
                        yield Settle()
                        index = sim.pc.CIA.value//4

                        terminated = yield issuer.dbg.terminated_o
                        print("terminated", terminated)

                        if index >= len(instructions):
                            print ("index over, send dmi stop")
                            # stop at end
                            yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
                            yield
                            yield

                        # wait one cycle for registers to settle
                        yield
                        yield

                    # wait one cycle for registers to settle
                    yield

                        # register check
                        yield from check_regs(self, sim, core, test, code)

                        # Memory check
                        yield from check_sim_memory(self, l0, sim, code)

                        terminated = yield issuer.dbg.terminated_o
                        print("terminated(2)", terminated)
                        if terminated:
                            break

                    # stop at end
                    yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
                    yield
                    yield

                    # get CR
                    cr = yield from get_dmi(dmi, DBGCore.CR)
                    print("after test %s cr value %x" % (test.name, cr))

                    # get XER
                    xer = yield from get_dmi(dmi, DBGCore.XER)
                    print("after test %s XER value %x" % (test.name, xer))

                    # test of dmi reg get
                    for int_reg in range(32):
                        yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
                        value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)

                        print("after test %s reg %2d value %x" %
                              (test.name, int_reg, value))

        styles = {
            'dec': {'base': 'dec'},

Return to bug 635

Lines 198-328 class TestRunner(FHDLTestCase): Link Here

(-)a/src/soc/simple/test/test_runner.py (-113 / +113 lines)
198		198
199	print(test.name)	199	print(test.name)
200	program = test.program	200	program = test.program
201	self.subTest(test.name)	201	with self.subTest(test.name):
202	print("regs", test.regs)	202	print("regs", test.regs)
203	print("sprs", test.sprs)	203	print("sprs", test.sprs)
204	print("cr", test.cr)	204	print("cr", test.cr)
205	print("mem", test.mem)	205	print("mem", test.mem)
206	print("msr", test.msr)	206	print("msr", test.msr)
207	print("assem", program.assembly)	207	print("assem", program.assembly)
208	gen = list(program.generate_instructions())	208	gen = list(program.generate_instructions())
209	insncode = program.assembly.splitlines()	209	insncode = program.assembly.splitlines()
210	instructions = list(zip(gen, insncode))	210	instructions = list(zip(gen, insncode))
211		211
212	# set up the Simulator (which must track TestIssuer exactly)	212	# set up the Simulator (which must track TestIssuer exactly)
213	sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,	213	sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
214	test.msr,	214	test.msr,
215	initial_insns=gen, respect_pc=True,	215	initial_insns=gen, respect_pc=True,
216	disassembly=insncode,	216	disassembly=insncode,
217	bigendian=bigendian,	217	bigendian=bigendian,
218	initial_svstate=test.svstate)	218	initial_svstate=test.svstate)
219		219
220	# establish the TestIssuer context (mem, regs etc)	220	# establish the TestIssuer context (mem, regs etc)
221		221
222	pc = 0 # start address	222	pc = 0 # start address
223	counter = 0 # test to pause/start	223	counter = 0 # test to pause/start
224		224
225	yield from setup_i_memory(imem, pc, instructions)	225	yield from setup_i_memory(imem, pc, instructions)
226	yield from setup_test_memory(l0, sim)	226	yield from setup_test_memory(l0, sim)
227	yield from setup_regs(pdecode2, core, test)	227	yield from setup_regs(pdecode2, core, test)
228		228
229	# set PC and SVSTATE	229	# set PC and SVSTATE
230	yield pc_i.eq(pc)	230	yield pc_i.eq(pc)
231	yield issuer.pc_i.ok.eq(1)	231	yield issuer.pc_i.ok.eq(1)
232		232
233	initial_svstate = test.svstate	233	initial_svstate = test.svstate
234	if isinstance(initial_svstate, int):	234	if isinstance(initial_svstate, int):
235	initial_svstate = SVP64State(initial_svstate)	235	initial_svstate = SVP64State(initial_svstate)
236	yield svstate_i.eq(initial_svstate.spr.value)	236	yield svstate_i.eq(initial_svstate.spr.value)
237	yield issuer.svstate_i.ok.eq(1)	237	yield issuer.svstate_i.ok.eq(1)
238	yield	238	yield
239
240	print("instructions", instructions)
241
242	# run the loop of the instructions on the current test
243	index = sim.pc.CIA.value//4
244	while index < len(instructions):
245	ins, code = instructions[index]
246
247	print("instruction: 0x{:X}".format(ins & 0xffffffff))
248	print(index, code)
249
250	if counter == 0:
251	# start the core
252	yield
253	yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
254	yield issuer.pc_i.ok.eq(0) # no change PC after this
255	yield issuer.svstate_i.ok.eq(0) # ditto
256	yield
257	yield
258		239
259	counter = counter + 1	240	print("instructions", instructions)
260		241
261	# wait until executed	242	# run the loop of the instructions on the current test
262	# wait for insn_done high
263	while not (yield issuer.insn_done):
264	yield
265	# wait for insn_done low
266	while (yield issuer.insn_done):
267	yield
268
269	# set up simulated instruction (in simdec2)
270	try:
271	yield from sim.setup_one()
272	except KeyError: # indicates instruction not in imem: stop
273	break
274	yield Settle()
275
276	# call simulated operation
277	print("sim", code)
278	yield from sim.execute_one()
279	yield Settle()
280	index = sim.pc.CIA.value//4	243	index = sim.pc.CIA.value//4
281		244	while index < len(instructions):
282	terminated = yield issuer.dbg.terminated_o	245	ins, code = instructions[index]
283	print("terminated", terminated)	246
284		247	print("instruction: 0x{:X}".format(ins & 0xffffffff))
285	if index >= len(instructions):	248	print(index, code)
286	print ("index over, send dmi stop")	249
287	# stop at end	250	if counter == 0:
288	yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)	251	# start the core
		252	yield
		253	yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
		254	yield issuer.pc_i.ok.eq(0) # no change PC after this
		255	yield issuer.svstate_i.ok.eq(0) # ditto
		256	yield
		257	yield
		258
		259	counter = counter + 1
		260
		261	# wait until executed
		262	# wait for insn_done high
		263	while not (yield issuer.insn_done):
		264	yield
		265	# wait for insn_done low
		266	while (yield issuer.insn_done):
		267	yield
		268
		269	# set up simulated instruction (in simdec2)
		270	try:
		271	yield from sim.setup_one()
		272	except KeyError: # indicates instruction not in imem: stop
		273	break
		274	yield Settle()
		275
		276	# call simulated operation
		277	print("sim", code)
		278	yield from sim.execute_one()
		279	yield Settle()
		280	index = sim.pc.CIA.value//4
		281
		282	terminated = yield issuer.dbg.terminated_o
		283	print("terminated", terminated)
		284
		285	if index >= len(instructions):
		286	print ("index over, send dmi stop")
		287	# stop at end
		288	yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
		289	yield
		290	yield
		291
		292	# wait one cycle for registers to settle
289	yield	293	yield
290	yield
291
292	# wait one cycle for registers to settle
293	yield
294		294
295	# register check	295	# register check
296	yield from check_regs(self, sim, core, test, code)	296	yield from check_regs(self, sim, core, test, code)
297		297
298	# Memory check	298	# Memory check
299	yield from check_sim_memory(self, l0, sim, code)	299	yield from check_sim_memory(self, l0, sim, code)
300		300
301	terminated = yield issuer.dbg.terminated_o	301	terminated = yield issuer.dbg.terminated_o
302	print("terminated(2)", terminated)	302	print("terminated(2)", terminated)
303	if terminated:	303	if terminated:
304	break	304	break
305		305
306	# stop at end	306	# stop at end
307	yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)	307	yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
308	yield	308	yield
309	yield	309	yield
310		310
311	# get CR	311	# get CR
312	cr = yield from get_dmi(dmi, DBGCore.CR)	312	cr = yield from get_dmi(dmi, DBGCore.CR)
313	print("after test %s cr value %x" % (test.name, cr))	313	print("after test %s cr value %x" % (test.name, cr))
314		314
315	# get XER	315	# get XER
316	xer = yield from get_dmi(dmi, DBGCore.XER)	316	xer = yield from get_dmi(dmi, DBGCore.XER)
317	print("after test %s XER value %x" % (test.name, xer))	317	print("after test %s XER value %x" % (test.name, xer))
318		318
319	# test of dmi reg get	319	# test of dmi reg get
320	for int_reg in range(32):	320	for int_reg in range(32):
321	yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)	321	yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
322	value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)	322	value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
323		323
324	print("after test %s reg %2d value %x" %	324	print("after test %s reg %2d value %x" %
325	(test.name, int_reg, value))	325	(test.name, int_reg, value))
326		326
327	styles = {	327	styles = {
328	'dec': {'base': 'dec'},	328	'dec': {'base': 'dec'},

Lines 13-27 import sys Link Here

(-)a/src/soc/simple/test/test_issuer.py (-16 / +16 lines)
13	from soc.simple.test.test_runner import TestRunner	13	from soc.simple.test.test_runner import TestRunner
14		14
15	# test with ALU data and Logical data	15	# test with ALU data and Logical data
16	from soc.fu.alu.test.test_pipe_caller import ALUTestCase	16	#from soc.fu.alu.test.test_pipe_caller import ALUTestCase
17	from soc.fu.div.test.test_pipe_caller import DivTestCases	17	#from soc.fu.div.test.test_pipe_caller import DivTestCases
18	from soc.fu.logical.test.test_pipe_caller import LogicalTestCase	18	#from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
19	from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase	19	#from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
20	from soc.fu.cr.test.test_pipe_caller import CRTestCase	20	#from soc.fu.cr.test.test_pipe_caller import CRTestCase
21	# from soc.fu.branch.test.test_pipe_caller import BranchTestCase	21	from soc.fu.branch.test.test_pipe_caller import BranchTestCase
22	# from soc.fu.spr.test.test_pipe_caller import SPRTestCase	22	# from soc.fu.spr.test.test_pipe_caller import SPRTestCase
23	from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase	23	#from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
24	from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)	24	#from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
25	# from soc.simulator.test_helloworld_sim import HelloTestCases	25	# from soc.simulator.test_helloworld_sim import HelloTestCases
26		26
27		27
Lines 37-51 if __name__ == "__main__": Link Here
37	unittest.main(exit=False)	37	unittest.main(exit=False)
38	suite = unittest.TestSuite()	38	suite = unittest.TestSuite()
39	# suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))	39	# suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))
40	suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))	40	#suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
41	# suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))	41	# suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))
42	suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))	42	#suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))
43	suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))	43	#suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
44	suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))	44	#suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
45	suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))	45	#suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
46	suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))	46	#suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
47	suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))	47	#suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
48	# suite.addTest(TestRunner(BranchTestCase.test_data, svp64=svp64))	48	suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64))
49	# suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))	49	# suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))
50		50
51	runner = unittest.TextTestRunner()	51	runner = unittest.TextTestRunner()