Attachment #99 for bug #484

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Lines 119-124 architecture behave of core is Link Here

(-)a/core.vhdl (-9 / +20 lines)
119	signal dbg_core_rst: std_ulogic;	119	signal dbg_core_rst: std_ulogic;
120	signal dbg_icache_rst: std_ulogic;	120	signal dbg_icache_rst: std_ulogic;
121		121
		122	-- CR register read port
		123	dbg_cr_req : out std_ulogic;
		124	dbg_cr_ack : in std_ulogic;
		125	dbg_cr_data : in std_ulogic_vector(32 downto 0);
		126
122	signal dbg_gpr_req : std_ulogic;	127	signal dbg_gpr_req : std_ulogic;
123	signal dbg_gpr_ack : std_ulogic;	128	signal dbg_gpr_ack : std_ulogic;
124	signal dbg_gpr_addr : gspr_index_t;	129	signal dbg_gpr_addr : gspr_index_t;
Lines 292-297 begin Link Here
292	clk => clk,	297	clk => clk,
293	d_in => decode2_to_cr_file,	298	d_in => decode2_to_cr_file,
294	d_out => cr_file_to_decode2,	299	d_out => cr_file_to_decode2,
		300	dbg_cr_req => dbg_cr_req,
		301	dbg_cr_ack => dbg_cr_ack,
		302	dbg_cr_data => dbg_cr_data,
295	w_in => writeback_to_cr_file,	303	w_in => writeback_to_cr_file,
296	sim_dump => sim_cr_dump,	304	sim_dump => sim_cr_dump,
297	log_out => log_data(184 downto 172)	305	log_out => log_data(184 downto 172)
Lines 403-417 begin Link Here
403	terminate => terminate,	411	terminate => terminate,
404	core_stopped => dbg_core_is_stopped,	412	core_stopped => dbg_core_is_stopped,
405	nia => fetch1_to_icache.nia,	413	nia => fetch1_to_icache.nia,
406	msr => msr,	414	msr => msr,
407	dbg_gpr_req => dbg_gpr_req,	415	dbg_cr_req => dbg_cr_req,
408	dbg_gpr_ack => dbg_gpr_ack,	416	dbg_cr_ack => dbg_cr_ack,
409	dbg_gpr_addr => dbg_gpr_addr,	417	dbg_cr_data => db_cr_data,
410	dbg_gpr_data => dbg_gpr_data,	418	dbg_gpr_req => dbg_gpr_req,
411	log_data => log_data,	419	dbg_gpr_ack => dbg_gpr_ack,
412	log_read_addr => log_rd_addr,	420	dbg_gpr_addr => dbg_gpr_addr,
413	log_read_data => log_rd_data,	421	dbg_gpr_data => dbg_gpr_data,
414	log_write_addr => log_wr_addr,	422	log_data => log_data,
		423	log_read_addr => log_rd_addr,
		424	log_read_data => log_rd_data,
		425	log_write_addr => log_wr_addr,
415	terminated_out => terminated_out	426	terminated_out => terminated_out
416	);	427	);
417		428

Lines 39-44 entity core_debug is Link Here

(-)a/core_debug.vhdl (+5 lines)
39	dbg_gpr_addr : out gspr_index_t;	39	dbg_gpr_addr : out gspr_index_t;
40	dbg_gpr_data : in std_ulogic_vector(63 downto 0);	40	dbg_gpr_data : in std_ulogic_vector(63 downto 0);
41		41
		42	-- CR register read port
		43	dbg_cr_req : out std_ulogic;
		44	dbg_cr_ack : in std_ulogic;
		45	dbg_cr_data : in std_ulogic_vector(32 downto 0);
		46
42	-- Core logging data	47	-- Core logging data
43	log_data : in std_ulogic_vector(255 downto 0);	48	log_data : in std_ulogic_vector(255 downto 0);
44	log_read_addr : in std_ulogic_vector(31 downto 0);	49	log_read_addr : in std_ulogic_vector(31 downto 0);

Lines 19-24 entity cr_file is Link Here

(-)a/cr_file.vhdl (+13 lines)
19		19
20	w_in : in WritebackToCrFileType;	20	w_in : in WritebackToCrFileType;
21		21
		22	dbg_cr_req : out std_ulogic;
		23	dbg_cr_ack : in std_ulogic;
		24	dbg_cr_data : in std_ulogic_vector(32 downto 0);
		25
22	-- debug	26	-- debug
23	sim_dump : in std_ulogic;	27	sim_dump : in std_ulogic;
24		28
Lines 82-87 begin Link Here
82	d_out.read_xerc_data <= xerc_updated;	86	d_out.read_xerc_data <= xerc_updated;
83	end process;	87	end process;
84		88
		89	dbg_cr_read_0: process(all)
		90	begin
		91	if dbg_cr_req = '1' then
		92	report "Reading CR " & to_hstring(crs_updated)
		93	end if;
		94	dbg_cr_data <= crs_updated;
		95	dbg_cr_ack <= '1';
		96	end process;
		97
85	sim_dump_test: if SIM generate	98	sim_dump_test: if SIM generate
86	dump_cr: process(all)	99	dump_cr: process(all)
87	begin	100	begin

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