| Summary: | implement CRweird instructions in ISACaller | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | andy.miroshnikov, libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| URL: | https://libre-soc.org/openpower/sv/cr_int_predication/ | ||
| See Also: |
https://bugs.libre-soc.org/show_bug.cgi?id=1009 https://bugs.libre-soc.org/show_bug.cgi?id=1011 |
||
| NLnet milestone: | NLnet.2022-08-107.ongoing | total budget (EUR) for completion of task and all subtasks: | 3000 |
| budget (EUR) for this task, excluding subtasks' budget: | 3000 | parent task for budget allocation: | 1027 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: |
jacob=800
lkcl=2200
|
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| Bug Depends on: | |||
| Bug Blocks: | 1067 | ||
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Description
Luke Kenneth Casson Leighton
2023-03-17 09:50:44 GMT
toshaan the pseudocode in draft form is designed already, the insteuctiins themselves designed already, it is a matter of nailing down the fields.txt (power isa book I section 1.6) the CSV files (microwatt style decoder) writing the pseudocode and writing the unit tests. the IRC discussion was here https://libre-soc.org/irclog/%23libre-soc.2023-03-15.log.html#t2023-03-15T16:55:02 which gives so many other examples when things were added that it really should be a "by-the-numbers" task, now. we can add a paid task if you are interested in updating the wiki https://libre-soc.org/docs/adding_instr/ https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isatables;hb=HEAD csvs, fields.txt pseodocode best in its own new subfile although a case could be made for adding them to condition.mdwn the fact that mtcr etc are not in that but are in the system chapter of Power ISA... https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD the ones involving RT-CRs need a workaround in ISACaller, i will have to handle that, but the actual scalar implementation is dead-straightforward. i have been editing this page so as to create ls015 https://libre-soc.org/openpower/sv/cr_int_predication/ also needed the two Forms as part of the RFC so that bit is done. commit f817539cbfb4fa73153369ce0f2ed9d1c23fca46 (HEAD -> master, origin/master) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Tue Apr 25 18:36:31 2023 +0100 add CW and CW2 Form needed for both #1035 and #1067 |