Bug 107

Summary:	IEEE754 FPU FCVT "downconversion" needed
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	ALU (including IEEE754 16/32/64-bit FPU)	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	PAYMENTPENDING FIXED
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
NLnet milestone:	NLnet.2019.02.012	total budget (EUR) for completion of task and all subtasks:	750
budget (EUR) for this task, excluding subtasks' budget:	750	parent task for budget allocation:	48
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:	"lkcl"={amount=750, paid=2019-07-10}
Bug Depends on:
Bug Blocks:	48

Description Luke Kenneth Casson Leighton 2019-07-10 09:57:59 BST

FP conversion from larger-sized FP numbers to smaller-sized ones
is needed: FP64->FP32, FP64->FP16, FP32->FP16.  unit tests also
needed, with full (comprehensive) coverage.

Comment 1 Luke Kenneth Casson Leighton 2019-07-10 10:01:17 BST

last unit test added, all covered:
https://git.libre-riscv.org/?p=ieee754fpu.git;a=commitdiff;h=ff5df25d28e88a15edee6d72e29c54fe105672e3