| Summary: | Generating a Libre-SOC Microwatt-compatible core with SVP64 | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Andrey Miroshnikov <andy.miroshnikov> |
| Component: | Source Code | Assignee: | Andrey Miroshnikov <andy.miroshnikov> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs, lkcl |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| URL: | https://libre-soc.org/HDL_workflow/gen_core_with_svp64/ | ||
| See Also: | https://bugs.libre-soc.org/show_bug.cgi?id=1146 | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | 1086 | ||
| Bug Blocks: | 961, 1129 | ||
| Attachments: |
Diff of mw vs mw+svp64 core using yosys ls
Shows full log of ls2 synthesis |
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Description
Andrey Miroshnikov
2023-08-01 12:45:41 BST
Created attachment 196 [details]
Shows full log of ls2 synthesis
Next step was to place the generated core inside the ls2 peripheral framework and create an FPGA image.
During the yosys synthesis, I encountered many combinatorial loops, which caused the timing analysis to fail. The errors mostly occurred in dec2, specifically the sv blocks.
Full log is attached.
(In reply to Andrey Miroshnikov from comment #1) > caused the timing analysis to fail. The errors mostly occurred in dec2, > specifically the sv blocks. ignore them 100%. p.s now you know why we cannot use DDR3 and instead use HyperRAM which can run as low as a 1 mhz clockrate. ah: it's an error not a warning. answer: i don't know. this code was written 18+ months ago. you'll have to investigate step-by-step, first listing actually what the loops are. As you have suggested yesterday Luke, I tried running this mw+svp64 libre-soc core within microwatt repo's verilator, and it runs hello world! Also started documenting the steps required to generate this core (still in progress): https://libre-soc.org/HDL_workflow/gen_core_with_svp64/ From the assembly file in hello world, I see that an instruction can be called by the machine code directly, https://git.libre-soc.org/?p=microwatt.git;a=blob;f=hello_world/head.S;h=63576063f040c707d307a6c0ea4216e16f3f2da9;hb=refs/heads/verilator_trace#l20 Now I'll need to play with pypowersim to make some svp64 machine code, which I could then insert into the hello world code and try running it. (In reply to Andrey Miroshnikov from comment #4) > As you have suggested yesterday Luke, I tried running this mw+svp64 > libre-soc core within microwatt repo's verilator, and it runs hello world! hooray. so now you know, there is a bug in the version of yosys you used to do the nextpnr-routing. verilator could not do a simulation if there was *actually* a combinatorial loop. > Also started documenting the steps required to generate this core (still in > progress): https://libre-soc.org/HDL_workflow/gen_core_with_svp64/ awesome. > From the assembly file in hello world, I see that an instruction can be > called by the machine code directly, > https://git.libre-soc.org/?p=microwatt.git;a=blob;f=hello_world/head.S; of course it can. that is what has been done for nearly 3 years now, back when lauri first did the a/v mp3 work. > Now I'll need to play with pypowersim to make some svp64 machine code, which > I could then insert into the hello world code and try running it. link it as a single static .o exactly as is done in media/ and you should be done in well under 2 hours. not one month of failing because you're not asking for guidance and think that the goal is "i have to do this entirely by myself". also examine konstantinos's crypto/ work as he combines assembly functions with c functions. this is the calling convention match up the registers declare a static header file BAM job is done. https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=media/calling-conv;hb=HEAD this is all extremely straightforward been done multiple times you just need to get on with it. |