| Summary: | Tasks required for ls2 soc peripheral interconnect on FPGA | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Andrey Miroshnikov <andy.miroshnikov> |
| Component: | Source Code | Assignee: | Andrey Miroshnikov <andy.miroshnikov> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs, lkcl |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | 1086, 1127 | ||
| Bug Blocks: | 1037 | ||
|
Description
Andrey Miroshnikov
2023-08-02 19:23:59 BST
At present, one can follow the ls2 tutorial: https://libre-soc.org/HDL_workflow/ls2/ to synthesise a bitstream for the Arty A7-100t to run a hello world C code. Other than this, micropython nor Linux kernel have been run (or at least documented on the wiki). |