Bug 1213

Summary: Using the ECP5 for Libre-SOC prototyping - FOSDEM 2024 by Tobias Platen
Product: Libre-SOC's first SoC Reporter: Tobias Platen <libre-soc>
Component: ConferencesAssignee: Tobias Platen <libre-soc>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-bugs, lkcl
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Other   
URL: https://fosdem.org/2024/schedule/event/fosdem-2024-2060-using-the-ecp5-for-libre-soc-prototyping/
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Bug Depends on:    
Bug Blocks: 1070    

Description Tobias Platen 2023-11-25 19:36:48 GMT 
I drafted my first proposal for a talk at FOSDEM:

The Libre-SOC project has been prototyped using an Lattic ECP5 FPGA before
its first [tapeout](https://libre-soc.org/180nm_Oct2020). 
Since then many things have changed. One big change is the use of a different
controller for DDR3 controller called [gram](https://git.libre-soc.org/?p=gram.git).
To get DDR3 working on the OrangeCrab many changes are needed.

This talk will provide an overview on my work on libre-soc in the past two years,
an overview of DDR SDRAM interfaces and the PHYs commonly found on FPGAs and some
ways to debug the OrangeCrab using a (BeagleWire)[https://www.crowdsupply.com/qwerty-embedded-design/beaglewire]
Comment 1 Luke Kenneth Casson Leighton 2023-11-25 19:46:18 GMT 
brilliant tobias, submit it here well before 1st dec
https://pretalx.fosdem.org/fosdem-2024/cfp
Comment 2 Tobias Platen 2023-11-26 18:40:58 GMT 
Submitted, sent mail
Comment 4 Luke Kenneth Casson Leighton 2023-12-04 15:56:28 GMT 
(In reply to Tobias Platen from comment #3)
> https://pretalx.fosdem.org/fosdem-2024/talk/review/
> XHGZGAZZTMSM8FC3X3SNBFM3EYEQ3NDT

tobias i did a quick review it looks great, we do however have to cut back
time as there is only half a day available and there are 10 (ten!) talks.
can you manage in under 25 minutes *including 5 for questions*?
Comment 5 Tobias Platen 2023-12-04 18:57:02 GMT 
No problem for me, I can shorten my talk.