Bug 124

Summary: add dynamically removable/insertable pipeline registers to div pipe to allow high clock speeds
Product: Libre-SOC's first SoC Reporter: Jacob Lifshay <programmerjake>
Component: ALU (including IEEE754 16/32/64-bit FPU)Assignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: All   
OS: All   
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Bug Depends on:    
Bug Blocks: 116    

Description Jacob Lifshay 2019-07-28 23:25:23 BST
see second half of http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-July/002218.html