| Summary: | Rc=1 vector output of CRs is going solely into CR0 | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs, programmerjake |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 676 | ||
this needs fixing in power_decoder2.py for i, stuff in enumerate(( ("RA", e.read_reg1, dec_a.reg_out, in1_svdec, in1_step, False), ("RB", e.read_reg2, dec_b.reg_out, in2_svdec, in2_step, False), ("RC", e.read_reg3, dec_c.reg_out, in3_svdec, in3_step, False), ("RT", e.write_reg, dec_o.reg_out, o_svdec, o_step, True), ("EA", e.write_ea, dec_o2.reg_out, o2_svdec, o2_step, True))): RT and EA. also needed vector of CRs with m.If(cr.sv_override == 1): # CR0 offs = SVP64CROffs.CR0 comb += to_reg.data.eq(step+offs)