Bug 136

Summary:	partitioned multiplier needs to be adapted to Dadda algorithm
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	ALU (including IEEE754 16/32/64-bit FPU)	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
NLnet milestone:	---	total budget (EUR) for completion of task and all subtasks:	0
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Bug Depends on:
Bug Blocks:	48

Description Luke Kenneth Casson Leighton 2019-08-31 09:28:50 BST

the wallace multiplier produces a 10-stage-long chain at 64-bit.
dadda tree multipliers use less gates.
https://github.com/jorisvr/gen_hdl_multiplier

existing code that needs converting:
https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part_mul_add/multiply.py;hb=HEAD