| Summary: | Implement MESA 3D Vulkan Driver NLNet 2019-10-042 | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Milestones | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | 2019-10P, addw, joost, libre-soc-bugs, programmerjake |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| URL: | https://libre-soc.org/nlnet_2019_amdvlk_port/ | ||
| NLnet milestone: | NLNet.2019.10.042.Vulkan | total budget (EUR) for completion of task and all subtasks: | 50000 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | 251 252 253 254 255 | The table of payments (in EUR) for this task; TOML format: | |
| Bug Depends on: | 53, 253, 260, 386, 405, 251, 252, 254, 255 | ||
| Bug Blocks: | 938 | ||
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Description
Luke Kenneth Casson Leighton
2019-10-03 08:25:57 BST
* create a 3D driver that "works with LLVM-IR and is effectively a portable software-only driver", very similar to SwiftShader. this would be estimated (as a major milestone) around 3-4 months. * (working closely with Jacob) identify the instructions which, if added, would accelerate 3D rendering, and arrange to use them in both the Mesa NIR *and* make sure that the LLVM-IR compiler recognises them. Schedule A for MoU 2019-10-042 # Initial Software-only 3D MESA Driver software only (SwiftShader style) 3D MESA Driver, portable (x86 etc) using non-accelerated LLVM Budget: EUR 12000 URL: http://bugs.libre-riscv.org/show_bug.cgi?id=251 # 3D accelerated opcodes need to be added to the POWER ISA simulator adding iterated support for 3D opcodes to ISA Simulator (and unit tests) Budget: EUR 7000 URL: http://bugs.libre-riscv.org/show_bug.cgi?id=252 # Add hardware implementations of 3D accelerated opcodes first iterative effort developing and adding hardware accelerated 3D opcodes to 3D MESA driver Budget: EUR 12500 URL: http://bugs.libre-riscv.org/show_bug.cgi?id=253 # 2nd iteration of opcodes in 3D MESA driver A 2nd iteration of opcodes in 3D MESA driver is needed. This involves assessing and reporting on the level of success of the first round of simulations and ease of implementability in hardware, as well as the effectiveness in number of gates, power consumption and (learning from Jeff Bush's Nyuzi work) the number of pixels processed per clock. Budget: EUR 12500 URL: http://bugs.libre-riscv.org/show_bug.cgi?id=254 # Second iteration round for opcodes, simulation and hardware for 3D MESA Documentation to the level of an ISA Standards Proposal of all hardware opcodes Budget: 6000 URL: http://bugs.libre-riscv.org/show_bug.cgi?id=255 note that bug #53 has budget from NLNet 2019-02-012 which should not duplicate here. #53 is primarily for Kazan however the HW can be used here as well obvioudly Software Dependencies: * All software build dependencies of the MESA library (yes this itself is a large list) * latex (and, depending on Alain's preferences for GUI editors, potentially texstudio) * LibreSOC HDL and all LibreSoc build dependencies, which include yosys and nmigen * the gem5 POWER ISA simulator and its software build dependencies. everything that we need to modify will be on http://git.libre-riscv.org. Overview We have the unusual goal of developing not just a new 3D MESA driver: the hardware itself is being simultaneously developed in conjunction with the software driver. However before spending the time implementing full hardware (even in HDL), which will be emulated significantly slower than actual hardware, we need to implement - and test and evaluate - the planned instructions using an emulator, first. This significantly reduces both development time and cost, allowing fast iteration and evaluation. Once we are happy with the chosen hardware instructions at the simulation level, then we may move to implementing them in hardware. We will need to write full unit tests of both the hardware and also run software unit tests as best as practical on emulated hardware (knowing that it will be operating thousands to tens of thousands of times slower) and, if practical, running on an FPGA board. After the hardware-level simulation, if the gate count and estimated gate count is acceptable when compared to commercial GPUs, *and* the number of pixels generated per clock is at an acceptable commercial level, then we can consider the hardware and software part of the project to be completed. Until then, we iterate round the above, and, once completed, finish off by documenting the hardware instructions as an "ISA Extension" for POWER. |