| Summary: | Formal correctness framework is needed for Power ISA | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Formal Verification | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs, vivekvpandya |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| See Also: | https://bugs.libre-soc.org/show_bug.cgi?id=420 | ||
| NLnet milestone: | NLNet.2019.10.032.Formal | total budget (EUR) for completion of task and all subtasks: | 12000 |
| budget (EUR) for this task, excluding subtasks' budget: | 6550 | parent task for budget allocation: | 158 |
| child tasks for budget allocation: | 306 331 332 335 340 418 419 421 | The table of payments (in EUR) for this task; TOML format: |
red={amount=6550, submitted=2022-07-04, paid=2022-07-21}
|
| Bug Depends on: | 211, 306, 331, 332, 418, 419 | ||
| Bug Blocks: | 158 | ||
|
Description
Luke Kenneth Casson Leighton
2020-03-02 13:13:25 GMT
The Power ISA pipelines are done: ALU, Logical, CR, Branch, Shift, SPR, Mul, Trap - this can be considered completed. |