Bug 200

Summary: IEEE754 FPU Coriolis2 layout
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Hardware LayoutAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: Jean-Paul.Chaput, libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Linux   
NLnet milestone: NLNet.2019.02.029.Coriolis2 total budget (EUR) for completion of task and all subtasks: 7000
budget (EUR) for this task, excluding subtasks' budget: 7000 parent task for budget allocation: 138
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
lip6_donated_nlnet = { amount = 6250, submitted = 2022-08-26, paid = 2022-08-31 } [lkcl] amount = 750 submitted = 2021-12-09 paid = 2021-12-09
Bug Depends on:    
Bug Blocks: 138, 199, 204    

Description Luke Kenneth Casson Leighton 2020-03-02 17:00:34 GMT
layout of the IEEE754 FPU "Function Units" needed, as part of the 180nm ASIC in bug #199. these are to be done as reuseable blocks because several FPMUL blocks, several FPSQRT blocks etc. are needed per core, and they are very large.
Comment 1 Luke Kenneth Casson Leighton 2021-11-11 14:30:26 GMT
https://git.libre-soc.org/?p=soclayout.git;a=tree;f=experiments6;hb=HEAD

Jean-Paul this was at least successful and showed that a large layout
would be possible.  we also did the Dependency Matrices:
https://git.libre-soc.org/?p=soclayout.git;a=tree;f=experiments8;hb=HEAD

and also i recall we did a manual explicit positioning of large cells,
at the top level, to see how that went, with internal positioning done
in the large sub-cells.

i think we can close this one.