| Summary: | potential changes to LibreSOC HDL to suit coriolis2 | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Hardware Layout | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs, staf |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| See Also: |
https://bugs.libre-soc.org/show_bug.cgi?id=502 https://bugs.libre-soc.org/show_bug.cgi?id=620 |
||
| NLnet milestone: | NLNet.2019.02.029.Coriolis2 | total budget (EUR) for completion of task and all subtasks: | 6000 |
| budget (EUR) for this task, excluding subtasks' budget: | 6000 | parent task for budget allocation: | 138 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: |
lkcl={amount=3000, submitted=2021-04-24, paid=2021-04-24}
staf={amount=3000, submitted=2021-04-21, paid=2021-04-21}
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| Bug Depends on: | |||
| Bug Blocks: | 138 | ||
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Description
Luke Kenneth Casson Leighton
2020-03-02 17:15:55 GMT
although it was not coriolis2 specifically we have had to change the design for SRAM (litex) because the SRAM is a fixed block. additionally the way that pinouts work in niolib required some changes added a 4k SRAM instance over Wishbone, involved adding "blackbox" atteibute support to coriolis2 verilog and ilang respect cases on names, where vhdl does not. this is causing issues on cosimulation but also name clashes in the P&R. https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/37 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/36 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/35 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/34 also c4m-jtag by Staf included here, for the JTAG TAP interface, some debugging and support involved. |