Bug 203

Summary: potential improvements to coriolis2 for LibreSOC Layout
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Hardware LayoutAssignee: Jean-Paul Chaput <Jean-Paul.Chaput>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs, marie-minerve.louerat
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Linux   
NLnet milestone: NLNet.2019.02.029.Coriolis2 total budget (EUR) for completion of task and all subtasks: 7000
budget (EUR) for this task, excluding subtasks' budget: 7000 parent task for budget allocation: 138
child tasks for budget allocation: 329 The table of payments (in EUR) for this task; TOML format:
lip6_donated_nlnet = { amount = 7000, submitted = 2022-08-26, paid = 2022-08-31 }
Bug Depends on:    
Bug Blocks: 138    

Description Luke Kenneth Casson Leighton 2020-03-02 17:26:27 GMT 
coriolis2 was initially designed for small ASICs (50,000 gates).  it needs significant improvements to be suitable for use with LibreSOC due to its massive size (500,000 gates).  additionally, it would be useful to prepare for coriolis2 conversion and refactoring to use python3
Comment 1 Luke Kenneth Casson Leighton 2020-12-02 14:38:17 GMT 
brief notes: niolib was added and also a new router algorithm.
Comment 2 Luke Kenneth Casson Leighton 2020-12-03 13:47:45 GMT 
https://gitlab.lip6.fr/vlsi-eda/alliance/-/issues/3
Comment 3 Luke Kenneth Casson Leighton 2021-03-29 13:26:31 BST 
*huge* amount of work gone in here, including antenna, buffers, IO pad ring
redesign.