| Summary: | Transition from symbolic to real Cell Library for 180nm layout | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Hardware Layout | Assignee: | Staf Verhaegen <staf> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | Jean-Paul.Chaput, libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| NLnet milestone: | NLNet.2019.02.029.Coriolis2 | total budget (EUR) for completion of task and all subtasks: | 5000 |
| budget (EUR) for this task, excluding subtasks' budget: | 5000 | parent task for budget allocation: | 138 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: |
staf={amount=5000, paid=2021-04-23}
|
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| Bug Depends on: | 199, 200 | ||
| Bug Blocks: | 138 | ||
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Description
Luke Kenneth Casson Leighton
2020-03-02 17:31:47 GMT
Staf are you happy with this contingency budget? I will discuss this further with Jean-Paul. I want a solution where the design can be made open source and does not have to be done under NDA. (In reply to Staf Verhaegen from comment #3) > I will discuss this further with Jean-Paul. I want a solution where the > design can be made open source and does not have to be done under NDA. _great_. altered accordingly symbolic layout is now possible with FreePDK45. The FreePDK45 setup is a real layout in Coriolis terms, not symbolic layout. So to summarize. For the single core tape-out the transition from symbolic to real layout has been done. I have a library release for TSMC 0.18um, this contains fab data that is under NDA so can not be made public. To allow people in the public the redo the full flow with everything open the FreePDK45 PDKMaster release has been set up to do a real flow on the libreSOC prototype. It show the full flow to all people participating in the flow: * First there is a description of the technology in a PDKMaster source file: https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/master/c4m/pdk/freepdk45/pdkmaster.py * This technology setup file is used by c4m-flexcell to generate a standard cell library using PDKMaster: https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/master/c4m/pdk/freepdk45/flexlib_.py * Both the technology setup and the flexcell standard cell library are then exported to Coriolis python code: https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/master/scripts/export_coriolis.py * Finally this Coriolis setup in then used in a Coriolis flow to do synthesis and place and route: https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/freepdk_c4m45/coriolis2/settings.py;h=cc10a52e3b3968b41ae7b630624b0a6f5ed14398;hb=HEAD To run the FreePDK45 P&R yourself you don't need to redo these things yourself. * Setup up libre-soc development environment + Coriolis environment * Check out soclayout ( * Then you can run the flow with ./build_full.sh in either experiments9/freepdk_c4m45 (long) or experiments10_verilog/freepdk_c4m45 (faster). It currently still fails with an error in BigVia._doCutMatrix. I think this fulfills the requirement of this bug. (In reply to Staf Verhaegen from comment #7) > * Then you can run the flow with ./build_full.sh in either > experiments9/freepdk_c4m45 (long) or experiments10_verilog/freepdk_c4m45 > (faster). It currently still fails with an error in BigVia._doCutMatrix. yes, i found this too - it is however part of coriolis2 not freepdk_c4m45 > I think this fulfills the requirement of this bug. agreed. |