Bug 205

Summary: documentation of coriolis2 layout process for 180nm
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Hardware LayoutAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Linux   
URL: http://libre-soc.org/3d_gpu/layouts/coriolis2_180nm/
NLnet milestone: NLNet.2019.02.029.Coriolis2 total budget (EUR) for completion of task and all subtasks: 4000
budget (EUR) for this task, excluding subtasks' budget: 3800 parent task for budget allocation: 138
child tasks for budget allocation: 291 The table of payments (in EUR) for this task; TOML format:
lkcl = { amount = 3800, submitted = 2022-07-04, paid = 2022-07-21 }
Bug Depends on:    
Bug Blocks: 138    

Description Luke Kenneth Casson Leighton 2020-03-02 17:39:12 GMT 
this is important for maintenance purposes and for later ASICs as well as educational purposes.  the process and decisions on how the layout was done must be documented, here:
http://libre-soc.org/3d_gpu/layouts/coriolis2_180nm/
Comment 1 Luke Kenneth Casson Leighton 2022-07-04 10:05:57 BST 
links to other pages added, videos, explanation of JTAG, IOring,
importance of autogeneration.