Bug 239

Summary:	FP16 (and FP128) POWER Formal Standard proposal
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Specification	Assignee:	Alain D D Williams <addw>
Status:	RESOLVED FIXED
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
URL:	https://libre-soc.org/openpower/sv/svp64/
NLnet milestone:	NLNet.2019.10.046.Standards	total budget (EUR) for completion of task and all subtasks:	2500
budget (EUR) for this task, excluding subtasks' budget:	2500	parent task for budget allocation:	174
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:	addw = {amount=1250, submitted=2022-08-18, paid=2022-08-25} lkcl = { amount = 1250, submitted = 2022-06-25, paid = 2022-07-21 }
Bug Depends on:
Bug Blocks:	174

Description Luke Kenneth Casson Leighton 2020-03-13 12:54:52 GMT

A formal write-up of the augmentation of POWER ISA to switch on IEEE754 FP16 (also useable for  FP128) is needed, to be proposed to the OpenPOWER Foundation at a later date.

Comment 1 Luke Kenneth Casson Leighton 2020-12-02 15:13:22 GMT

we may actually do BF16 rather than FP128

Comment 2 Luke Kenneth Casson Leighton 2022-06-25 10:15:20 BST

this is done, the decision was to go with:

* default: FP64
* 0b01   : FP32
* 0b10   : FP16
* 0b11   : BF16

as part of the element-width overrides in SVP64

## Elwidth for FP Registers:

| Value | Mnemonic       | Description                        |
|-------|----------------|------------------------------------|
| 00    | DEFAULT        | default behaviour for FP operation     |
| 01    | `ELWIDTH=f32`  | 32-bit IEEE 754 Single floating-point  |
| 10    | `ELWIDTH=f16`  | 16-bit IEEE 754 Half floating-point   |
| 11    | `ELWIDTH=bf16` | Reserved for `bf16` |