Bug 249

Summary: Additional Wishbone B4 peripherals for Libre-SOC (including conversion from patented AXI4)
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
NLnet milestone: NLNet.2019.10.043.Wishbone total budget (EUR) for completion of task and all subtasks: 12500
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation: 175
child tasks for budget allocation: 468 795 797 801 806 The table of payments (in EUR) for this task; TOML format:
Bug Depends on: 803    
Bug Blocks: 175    

Description Luke Kenneth Casson Leighton 2020-03-13 15:11:39 GMT 
Seek out existing (non-streaming) Wishbone Master
and Slave Bus implementations (or implement them if necessary, or convert from AXI4 protocol), provide
formal proof unit tests of their correctness, and add additional example
peripherals.
See https://github.com/cocotb/cocotb/pull/439 in particular