Bug 252

Summary: 3D accelerated opcodes need to be added to the POWER ISA simulator
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
See Also: http://bugs.libre-riscv.org/show_bug.cgi?id=241
https://bugs.libre-soc.org/show_bug.cgi?id=896
https://bugs.libre-soc.org/show_bug.cgi?id=897
NLnet milestone: NLNet.2019.10.042.Vulkan total budget (EUR) for completion of task and all subtasks: 7000
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation: 140
child tasks for budget allocation: 896 898 899 The table of payments (in EUR) for this task; TOML format:
Bug Depends on:    
Bug Blocks: 140    

Description Luke Kenneth Casson Leighton 2020-03-13 15:36:02 GMT 
adding iterated support for 3D opcodes to ISA Simulator (and unit tests) is needed.  likely to be added to gem5.
Comment 1 Luke Kenneth Casson Leighton 2022-09-16 00:34:03 BST 
all sub-tasks completed 100%, closing this one.
RFPs are going in under *this* bugreport (252)