Bug 256

Summary: Enhancements to an OpenPOWER ISA-level Simulator are needed
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED DUPLICATE    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
NLnet milestone: NLNet.2019.10.046.Standards total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation:
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Description Luke Kenneth Casson Leighton 2020-03-13 18:26:47 GMT 
The vectorisation and other improvements needed for the LibreSOC need a simulator in order to test out applications at the assembly-code / binary level, prior to implementation in hardware.  An instruction-compatible simulator will be able to execute programs at reasonable speed whereas the hardware-level simulator will be hundreds of thousands of times slower.  gem5 is a suitable starting point, and the modifications to spike (RV simulator) need to be ported to it:
https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=tree;h=refs/heads/sv;hb=refs/heads/sv

see this:
https://www.gem5.org/documentation/general_docs/architecture_support/
Comment 1 Luke Kenneth Casson Leighton 2020-03-13 18:29:13 GMT 

*** This bug has been marked as a duplicate of bug 241 ***