Bug 289

Summary: LD/ST Function Unit address match "vector" optimisation
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
See Also: https://bugs.libre-soc.org/show_bug.cgi?id=216
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Description Luke Kenneth Casson Leighton 2020-04-20 10:10:43 BST 
at the L0 Cache/Buffer level, and in the address-match matrix, a massive
array of XOR gates (comparators) is needed.  this is a huge power drain.

however back at the vector-issue phase, information is known between
multiple units: there is a very high probability that related element
addresses will not have changed (especially on element-strided
LD/STs) and, furthermore, it is very easy to detect.

https://groups.google.com/d/msg/comp.arch/cbGAlcCjiZE/IDhmQPS6AAAJ

therefore as an enhancement, when Vector LD/STs are involved, provide
additional information down to the address-match and L0 cache/buffer
that saves huge amounts of power.