Bug 298

Summary:	consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
Product:	Libre-SOC's first SoC	Reporter:	Jacob Lifshay <programmerjake>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	All
OS:	All
NLnet milestone:	---	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
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Description Jacob Lifshay 2020-05-01 20:17:25 BST

combines binary adder with address decoder, saving a few gate delays.
https://en.wikipedia.org/wiki/Sum-addressed_decoder
The patents appear to have expired.

Comment 1 Luke Kenneth Casson Leighton 2020-05-02 00:21:10 BST

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006196.html