Bug 308

Summary:	POWER variable-length encoding scheme needed
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Specification	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-bugs, programmerjake
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=238
NLnet milestone:	NLNet.2019.10.046.Standards	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:	174
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:

Description Luke Kenneth Casson Leighton 2020-05-13 10:37:52 BST

instruction stream order needs to be sorted out so that the proposed
Compressed/48/64/VBLOCK encoding will fit.  currently, LE on POWER
is wholly unsuited to variable-length ISA encoding due to the opcode
being at the wrong end of a sequential instruction byte stream

https://libre-soc.org/openpower/

http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006553.html

Comment 1 Luke Kenneth Casson Leighton 2020-05-13 10:38:44 BST

note, not to be confused with bug #238 which is *actual* compressed
(16-bit) instruction encodings.