Bug 344

Summary: missing mtmsr and mfsprd
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Mac OS   
NLnet milestone: NLNet.2019.10.043.Wishbone total budget (EUR) for completion of task and all subtasks: 100
budget (EUR) for this task, excluding subtasks' budget: 100 parent task for budget allocation: 383
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
"lkcl"={amount=100, paid=2020-08-21}
Bug Depends on:    
Bug Blocks: 348, 383    

Description Luke Kenneth Casson Leighton 2020-05-24 15:27:44 BST 
missing two operations from sprset.mdwn and also minor_op31.csv

Move To Machine State Register
X-form

mtmsr RS,L
if L = 0 then
MSR48 ← (RS)48 | (RS)49
MSR58 <- ((RS)58 | (RS)49)& ¬(MSR41 & MSR3 & (¬(RS)49))
MSR59 <- ((RS)59 | (RS)49)& ¬(MSR41 & MSR3 & (¬(RS)49))
MSR32:40 42:47 49:50 52:57 60:62 <- (RS)32:40 42:47 49:50 52:57 60:62
else
MSR48 62 ← (RS)48 62

Move To Machine State Register Doubleword
X-Form

mtmsrd RS,L
if L = 0 then
MSR48 ← (RS)48 | (RS)49
MSR58 <- ((RS)58 | (RS)49)& ¬(MSR41 & MSR3 & (¬(RS)49))
MSR59 <- ((RS)59 | (RS)49) & ¬(MSR41 & MSR3 & (¬(RS)49))
MSR0:2 4:40 42:47 49:50 52:57 60:62 ← (RS)0:2 4 6:40 42:47 49:50 52:57 60:62 
else
MSR48 62 ← (RS)48 62

Move From Machine State Register X-form
mfmsr RT
RT ← MSR
Comment 1 Luke Kenneth Casson Leighton 2020-07-13 19:09:31 BST 
commit bd2acc23a6b1e4b2cb02bbdbf6f6ed776eb27ed9 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Mon Jul 13 19:07:08 2020 +0100

    add mtmsrd instruction and unit test