Bug 349

Summary: privileged-instruction decoding function needed
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: High    
Version: unspecified   
Hardware: PC   
OS: Mac OS   
NLnet milestone: NLNet.2019.10.043.Wishbone total budget (EUR) for completion of task and all subtasks: 100
budget (EUR) for this task, excluding subtasks' budget: 100 parent task for budget allocation: 383
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
lkcl = { amount = 100, submitted = 2020-12-06, paid = 2020-12-06 }
Bug Depends on:    
Bug Blocks: 383    

Description Luke Kenneth Casson Leighton 2020-05-24 22:51:22 BST 
certain operations are privileged.  in the decoder these need to be
marked as such, and a trap raised instead.

* implementation: done in PowerDecode2

* tested: OP_MFMSR       - pass trap pipe
* not tested: OP_MTMSRD  - pass trap pipe
* not tested: OP_MTMSR   - pass trap pipe
* not tested: OP_MTSPR   - spr pipe
* not tested: OP_MFSPR   - spr pipe
* not tested: OP_ATTN    - core/issuer
* tested: OP_RFID      - pass trap pipe

* test against qemu: not done
Comment 1 Luke Kenneth Casson Leighton 2020-05-24 22:51:56 BST 
from https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl

    type privilege_level is (USER, SUPER);
    type op_privilege_array is array(insn_type_t) of privilege_level;
    constant op_privilege: op_privilege_array := (
        OP_ATTN => SUPER,
        OP_MFMSR => SUPER,
        OP_MTMSRD => SUPER,
        OP_RFID => SUPER,
        others => USER
        );

    function instr_is_privileged(op: insn_type_t; insn: std_ulogic_vector(31 downto 0))
        return boolean is
    begin
        if op_privilege(op) = SUPER then
            return true;
        elsif op = OP_MFSPR or op = OP_MTSPR then
            return insn(20) = '1';
        else
            return false;
    end;
Comment 2 Luke Kenneth Casson Leighton 2020-07-12 19:28:45 BST 
note in spec:

• If spr0 = 0, the illegal instruction error handler is invoked.
• If spr0 = 1, the system privileged instruction error handler is invoked.

this needs to be done in PowerDecoder2 where the SPRMap exists
Comment 3 Luke Kenneth Casson Leighton 2020-07-14 01:58:52 BST 
need to read MSR, add extra read port to fastregs to get it.  pass in to PowerDecoder2 at issue time.

also, remove nia and XerBits at same time.
Comment 4 Luke Kenneth Casson Leighton 2020-07-14 13:00:38 BST 
commit a323d95f21b521d9fffd5ce3e180449815051d3a (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Jul 14 13:00:19 2020 +0100

    add in privileged instruction decision-making in PowerDecode2

commit 4c040d55af86f8cf94bb313aee5c5dece8fed916 (origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Jul 14 12:43:53 2020 +0100

    add MSR reading to issue FSM
Comment 5 Luke Kenneth Casson Leighton 2020-07-14 14:06:02 BST 
commit 7ca3ae564edf139d0c4abcc5c1996cd64138a87f (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Tue Jul 14 14:05:38 2020 +0100

    add priv instruction checking to ISACaller simulator
Comment 6 Luke Kenneth Casson Leighton 2020-07-15 16:24:17 BST 
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD#l45

TODO: shorten function by combining cases
Comment 7 Luke Kenneth Casson Leighton 2020-07-16 11:25:57 BST 
hmm can't use fu/spr/test/test_pipe_caller.py (or the compunit variant)
because for OP_MTSPR/MFSPR calling those instructions results in the
opcode being *changed* to OP_TRAP, which of course the SPR pipeline
doesn't support.

have to find a different way (global tests on the full compunit suite,
test_core.py, test_issuer.py etc.)