| Summary: | move RS to 1st or 2nd operand in CSV files | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Mac OS | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 305, 314, 330, 339 | ||
turns out we can't do this for SHIFT_ROT but it can be done for: * CR (for MTCRF) * ALU (for EXTS) * Logical (for a bunch of stuff) MUL and DIV pipelines also need checking: however these actually have 3-operand RA RB RC so it *may* not be applicable. |
we are doing this - a lot - i.e. in nearly every single Function Unit: # RA (or RC) reg3_ok = yield dec2.e.read_reg3.ok reg1_ok = yield dec2.e.read_reg1.ok assert reg3_ok != reg1_ok if reg3_ok: data1 = yield dec2.e.read_reg3.data res['a'] = sim.gpr(data1).value elif reg1_ok: data1 = yield dec2.e.read_reg1.data res['a'] = sim.gpr(data1).value if instead the CSV files *specified* that RS was in position (read_reg1) *already*, this would no longer be necessary. the same thing applies to ShiftRot - except this time RS and RB should be actually *swapped over*. this is quite a big change as it affects every single Function Unit, unit test, and formal proof.