| Summary: | improvements to nmigen and yosys | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| See Also: |
https://bugs.libre-soc.org/show_bug.cgi?id=622 https://bugs.libre-soc.org/show_bug.cgi?id=620 |
||
| NLnet milestone: | NLNet.2019.10.043.Wishbone | total budget (EUR) for completion of task and all subtasks: | 7000 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | 175 |
| child tasks for budget allocation: | 364 458 475 | The table of payments (in EUR) for this task; TOML format: | |
| Bug Depends on: | 364, 458 | ||
| Bug Blocks: | 175 | ||
|
Description
Luke Kenneth Casson Leighton
2020-06-04 14:40:01 BST
also needed is a way for yosys (or nmigen) to optimise out constants and unused signals... *without* requiring that the entire design be flattened. currently, coriolis2 has had to be significantly modified to cope with dangling (unused) connections. the design is too big to flatten so it is not appropriate to call yosys flatten. in a large OO design, module parameters can be Const or unused. when the design RTL is flattened this is not a problem. however without flattening yosys will *not* pass the Const parameter into the module and perform constant optimisation *in the module*, and it will *not* likewise remove unused outgoing signals *from* that module that are not externally connected to its parent. when such non-optimised non-flattened designs are passed to coriolis2 it causes problems because of dangling (unconnected) signals. two potential ways in which this can be fixed: in yosys, or on nmigen. see bug #458 some augmentations are needed to Value and UserValue in order to support alternative behaviour but keeping the standard nmigen API. cxxsim being used in gate-level simulation, some strange segfaulting going on, being sorted out by whitequark. example: https://github.com/YosysHQ/yosys/pull/2724 |