| Summary: | need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | RESOLVED DUPLICATE | ||
| Severity: | enhancement | CC: | libre-soc-bugs, mtnolan2640, postmaster |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Mac OS | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Luke Kenneth Casson Leighton
2020-06-08 19:34:03 BST
Cycle accurate - as in checking that the results are the same after every step? (In reply to Michael Nolan from comment #1) > Cycle accurate - as in checking that the results are the same after every > step? cycle-accurate means that yes, you _could_ check that the results are the same after every step through each and every instruction (not that you absolutely have to: it's just that it's possible to do so). a JIT compiler (pearpc's JIT, qemu JIT) that is very specifically *not* guaranteed to be the case, because several emulated instructions can end up being replaced by one (optimised) sequence of host-native instructions. JIT-translated code would clearly be absolutely useless for us to attempt to run and compare against, for that reason. spike (the RISC-V simulator) went to a lot of trouble to even maintain cycle-accurate emulation of the PTW, the MMU - pretty much everything, *specifically* so that the software (BBL, linux kernel etc.) could be worked on in parallel with development of some hardware, and the specification formalised even before that. powerpc64-linux-gnu-gdb -interpreter=mi ~-data-list-register-names ^done,register-names=["r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12","r13","r14","r15","r16","r17","r18","r19","r20","r21","r22","r23","r24","r25","r26","r27","r28","r29","r30","r31","f0","f1","f2","f3","f4","f5","f6","f7","f8","f9","f10","f11","f12","f13","f14","f15","f16","f17","f18","f19","f20","f21","f22","f23","f24","f25","f26","f27","f28","f29","f30","f31","pc","msr","cnd","lr","cnt","xer","fpscr","mq" that should do the trick. we can get at MSR, CR0-7 (cnd), XER, PC, LR, cnt is probably CTR, mq i have no idea. |