| Summary: | Investigate the possibility of implementing parts of OPENCAPI to supplement Wisbone vB4 | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Cole Poirier <colepoirier> |
| Component: | Specification | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | DEFERRED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs, programmerjake |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Cole Poirier
2020-06-10 23:25:59 BST
Not possible until after 28nm quadcore asic due to 25GHz clock requirement. 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm territory. (In reply to Luke Kenneth Casson Leighton from comment #2) > 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm > territory. I don't think that's actually true, all you need is a 25GHz PLL with a approx. 50% duty cycle and to use both negative and positive edge-triggered flip flops. (In reply to Jacob Lifshay from comment #3) > (In reply to Luke Kenneth Casson Leighton from comment #2) > > 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm > > territory. > > I don't think that's actually true, all you need is a 25GHz PLL with a > approx. 50% duty cycle and to use both negative and positive edge-triggered > flip flops. if you have gates and flip flops that are fast enough, you could even get away with a 12.5GHz PLL with a 90deg phase shifted output. (In reply to Jacob Lifshay from comment #3) > (In reply to Luke Kenneth Casson Leighton from comment #2) > > 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm > > territory. > > I don't think that's actually true, all you need is a 25GHz PLL with a > approx. 50% duty cycle and to use both negative and positive edge-triggered > flip flops. Ok so "Not possible until after 28nm quadcore asic due to 25GHz clock requirement." is accurate right? And this should remain a deferred bug report? Or should it be closed entirely? (In reply to Cole Poirier from comment #5) > (In reply to Jacob Lifshay from comment #3) > > (In reply to Luke Kenneth Casson Leighton from comment #2) > > > 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm > > > territory. > > > > I don't think that's actually true, all you need is a 25GHz PLL with a > > approx. 50% duty cycle and to use both negative and positive edge-triggered > > flip flops. > > Ok so "Not possible until after 28nm quadcore asic due to 25GHz clock > requirement." is accurate right? I'm not sure, it's probably possible due to only needing 25GHz signalling right at the I/O circuit, using 12.5GHz or slower everywhere else, but may be lots of effort due to the unusual design required. > And this should remain a deferred bug > report? Or should it be closed entirely? We can definitely use part of OpenCAPI's logical protocol without actually needing 25GHz signalling, so maybe defer till after the oct 2020 tapeout? definitely should not be closed based on 25GHz. (In reply to Jacob Lifshay from comment #6) > I'm not sure, it's probably possible due to only needing 25GHz signalling > right at the I/O circuit, using 12.5GHz or slower everywhere else, but may > be lots of effort due to the unusual design required. > > > And this should remain a deferred bug > > report? Or should it be closed entirely? > > We can definitely use part of OpenCAPI's logical protocol without actually > needing 25GHz signalling, so maybe defer till after the oct 2020 tapeout? > definitely should not be closed based on 25GHz. Cool! That's exactly what I was wondering about when I created this! :) Happy to hear that we can likely use the some part of the logical protocol before reaching 12.5GHz external PLLs. |