Bug 40

Summary: investigate STB/ACK delays
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: ALU (including IEEE754 16/32/64-bit FPU)Assignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
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Description Luke Kenneth Casson Leighton 2019-03-09 05:33:22 GMT
https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html

use of STB/ACK results in an extra clock cycle's delay (2 cycles total) between stages.  this needs to be dealt with and preferably removed entirely.