| Summary: | runtime configureable LoadStoreUnit needed | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Michael Nolan <mtnolan2640> |
| Status: | RESOLVED FIXED | ||
| Severity: | enhancement | CC: | libre-soc-bugs |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 393 | ||
|
Description
Luke Kenneth Casson Leighton
2020-06-24 15:56:58 BST
michael are you sure this is resolved, i didn't see a commit? did you remember to "git add"? forgot to add cross-ref: http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008354.html basic principle: class ConfigureableLoadStoreUnit: def __init__(self, ifacetype, *args, **kwargs): if ifacetype == "testmem": self.lsi = TestMemoryLoadStoreUnit(*args, **kwargs) elif ifacetype == "bare_wb": self.lsi = BareLoadStoreUnit(*args, **kwargs) elif ifacetype == "cache_wb": self.lsi = CacheLoadStoreUnit(*args, **kwargs) apologies, michael, i didn't hear back from you, had to move on: [master c88f971] add reconfigureable Load/Store class |