Bug 41

Summary:	share 2x 32 bit FMUL pipeline stages to create a 64 bit FMUL
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	ALU (including IEEE754 16/32/64-bit FPU)	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
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Description Luke Kenneth Casson Leighton 2019-03-09 05:36:11 GMT

to save on gates, the idea is to share a pair of 32-bit multiply stages to create 64-bit results.

this will likely require that a 64-bit FMUL be a variable-length pipeline, carrying out a matrix of HI-word / LO-word 32-bit multiplies and summing them.  if any permutation of HI/LO-word is zero, the actual 32-32-bit multiply need not be performed.