Bug 410

Summary:	Design Bus Protocol suitable for speculative execution
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	Other
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=397 https://bugs.libre-soc.org/show_bug.cgi?id=70
NLnet milestone:	NLNet.2019.10.043.Wishbone	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:	383
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:
Bug Depends on:
Bug Blocks:	383

Description Luke Kenneth Casson Leighton 2020-07-01 14:37:23 BST

Standard processor Bus APIs (Wishbone) operate on an atomic "take it or leave it" protocol.  This is unsuitable for speculative execution which needs a "Contract of Sale" protocol involving "offer, exchange, complete" that may be cancelled or declined.  This type of Bus Protocol therefore needs to be designed, implemented and documented.

Comment 1 Luke Kenneth Casson Leighton 2021-10-28 18:32:48 BST

thanks to octavius:
http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-October/003974.html