Bug 435

Summary:	PC and MSR need to be in the "state" (Decode2Execute1Type)
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Source Code	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	RESOLVED FIXED
Severity:	enhancement	CC:	libre-soc-bugs
Priority:	---
Version:	unspecified
Hardware:	PC
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=421 https://bugs.libre-soc.org/show_bug.cgi?id=325 https://bugs.libre-soc.org/show_bug.cgi?id=355 https://bugs.libre-soc.org/show_bug.cgi?id=348 https://bugs.libre-soc.org/show_bug.cgi?id=313
NLnet milestone:	NLNet.2019.10.043.Wishbone	total budget (EUR) for completion of task and all subtasks:	100
budget (EUR) for this task, excluding subtasks' budget:	100	parent task for budget allocation:	383
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:	lkcl={amount=100,paid=2020-08-19}
Bug Depends on:
Bug Blocks:	335, 383

Description Luke Kenneth Casson Leighton 2020-07-21 14:14:51 BST

to save on regfile ports, PC and MSR need to be pased in to
PowerDecode2 (MSR already is), and put into Decode2Execute1Type
then copied into XXX_input_record (CompXXXOpSubset) as appropriate.

this affects branch, trap and spr pipelines.