Bug 468

Summary: wishbone downconverter needed
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Linux   
NLnet milestone: NLNet.2019.10.043.Wishbone total budget (EUR) for completion of task and all subtasks: 200
budget (EUR) for this task, excluding subtasks' budget: 200 parent task for budget allocation: 249
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
lkcl = { amount = 200, submitted = 2020-12-06, paid = 2020-12-06 }
Bug Depends on:    
Bug Blocks: 11, 383    

Description Luke Kenneth Casson Leighton 2020-08-18 15:14:59 BST 
a downconverter is needed for master devices of width 128 or 64 to access 64 or 32 bit slaves.
Comment 1 Luke Kenneth Casson Leighton 2020-08-18 15:15:38 BST 
Misoc, written in migen, contains both an upconverter and downconverter.
Comment 2 Luke Kenneth Casson Leighton 2020-08-18 17:54:50 BST 
suggestion from Dagi on #nmigen:
https://github.com/ECP5-PCIe/ECP5-Utils/blob/master/utils.py