Bug 470

Summary: convert code using LoadStoreInterface to PortInterface
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: CONFIRMED ---    
Severity: enhancement CC: libre-soc-bugs
Priority: ---    
Version: unspecified   
Hardware: PC   
OS: Linux   
See Also: https://bugs.libre-soc.org/show_bug.cgi?id=756
NLnet milestone: NLNet.2019.10.043.Wishbone total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0 parent task for budget allocation:
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
Bug Depends on:    
Bug Blocks: 383    

Description Luke Kenneth Casson Leighton 2020-08-20 11:54:35 BST 
the converter pi2ls.py unfortunately involves an additional FSM that is
overhead (and causing problems).  a version of BareLoadStoreUnit is
needed that complies to PortInterface and accesses the wishbone bus
directly.

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/pimem.py;hb=HEAD#l35

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/loadstore.py;hb=HEAD#l13

also the Instruction Fetch unit can at some point be converted as well
although it is not as high priority as it is working.

the same unit tests currently in place can be used that are currently
testing PortInterface into small wishbone SRAM