Bug 476

Summary: addme ALU pipeline bug
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: RESOLVED FIXED    
Severity: enhancement CC: libre-soc-bugs, programmerjake
Priority: High    
Version: unspecified   
Hardware: PC   
OS: Linux   
See Also: https://bugs.libre-soc.org/show_bug.cgi?id=477
NLnet milestone: NLNet.2019.10.043.Wishbone total budget (EUR) for completion of task and all subtasks: 100
budget (EUR) for this task, excluding subtasks' budget: 100 parent task for budget allocation: 383
child tasks for budget allocation: The table of payments (in EUR) for this task; TOML format:
lkcl = { amount = 100, submitted = 2020-12-06, paid = 2020-12-06 }
Bug Depends on:    
Bug Blocks: 383    

Description Luke Kenneth Casson Leighton 2020-08-27 18:18:22 BST 
RA = 0x7ffffffff
CA = 1

result in simulation is that CA=1 but CA32=0

to be resolved: is this a simulator bug or is it an HDL error
Comment 1 Jacob Lifshay 2020-08-27 18:19:58 BST 
I can add this to power-instruction-analyzer
Comment 2 Luke Kenneth Casson Leighton 2020-08-27 20:38:37 BST 
simulator bug
commit 1fc2a159a3181ac77fe7156de7ca811d185548f9

resolved by special-casing OP_ADD
Comment 3 Luke Kenneth Casson Leighton 2020-08-27 20:53:21 BST 
commit f3b4db25993b9be457c0c0b87d2bfea78a83a247 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Thu Aug 27 20:52:58 2020 +0100

    xer so is not being passed through to CR0

another one in "addme."
Comment 4 Luke Kenneth Casson Leighton 2020-08-27 21:13:35 BST 
(In reply to Jacob Lifshay from comment #1)
> I can add this to power-instruction-analyzer

yes please, it's really quite frustrating, the sheer number of options.
Comment 5 Luke Kenneth Casson Leighton 2020-08-27 21:31:14 BST 
commit 9486ce5933b5a20031166a1caffa0821b2af883f (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Thu Aug 27 21:18:12 2020 +0100

    https://bugs.libre-soc.org/show_bug.cgi?id=476
    XER SO not being "listened" to correctly when OE=0 and Rc=1 creating CR0

jacob this was another (arbitrary) test, coming from microwatt:

        lst = ["addme. 6, 16"]
        initial_regs = [0] * 32
        initial_regs[16] = 0x7ffffffff
        initial_sprs = {}
        xer = SelectableInt(0, 64)
        xer[XER_bits['CA']] = 1
        xer[XER_bits['SO']] = 1