| Summary: | review ls180 reset connections | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Source Code | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs, staf |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | Other | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 383 | ||
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Description
Luke Kenneth Casson Leighton
2020-10-07 14:17:36 BST
Another thing to verify is that you don't depend on the verilog initial section. A difference between FPGA and ASIC is that most FPGAs embed the initial state of the registers in their bitstream and on ASIC registers will have a random value after power-up. Or said otherwise for ASICs setting a value of a register in the initial section is ignored. I guess, but am not 100% sure that in nmigen you can only have problems if you use reset_less signals as you will always assume a reset is applied to an ASIC after power-up. One of the problems is that pysim has the FPGA behaviour on reset_less signals and not the ASIC one. That was a few months ago so I don't know if that has changed. This means that pysim/cxxsim unit tests may not reveal problems for ASICs with reset_less signals. (In reply to Staf Verhaegen from comment #1) > I guess, but am not 100% sure that in nmigen you can only have problems if > you use reset_less signals as you will always assume a reset is applied to > an ASIC after power-up. One of the problems is that pysim has the FPGA > behaviour on reset_less signals and not the ASIC one. That was a few months > ago so I don't know if that has changed. This means that pysim/cxxsim unit > tests may not reveal problems for ASICs with reset_less signals. litex compiles with verilator, and that runs ok (although i did run into problems the first time, which i sorted). i've only used nmigen reset_less signals where it's known not to matter. thank you for highlighting this, it'll be something important to check. Resource about ASIC resets: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf |