| Summary: | Define JTAG pins and set up with litex for versa_ecp5 | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Cole Poirier <colepoirier> |
| Component: | Source Code | Assignee: | Cole Poirier <colepoirier> |
| Status: | RESOLVED DUPLICATE | ||
| Severity: | normal | CC: | libre-soc-bugs, lkcl |
| Priority: | Normal | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| See Also: | https://bugs.libre-soc.org/show_bug.cgi?id=517 | ||
| NLnet milestone: | NLNet.2019.10.043.Wishbone | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | 383 |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 383 | ||
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Description
Cole Poirier
2020-10-15 18:38:48 BST
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