| Summary: | analysis of former variant of SVPrefix to fit onto OpenPOWER with little-to-no modification | ||
|---|---|---|---|
| Product: | Libre-SOC's first SoC | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | Specification | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-isa |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
| Bug Depends on: | |||
| Bug Blocks: | 213 | ||
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Description
Luke Kenneth Casson Leighton
2020-11-28 15:15:44 GMT
the preliminary analysis to fit on top of the forms created for RV show that there is around a 90% match. things that do not fit or need further analysis: * st*x instructions (taking 3 read operands and stcix writing to CRs) * CRio operations (mcrxr and cr* ops) which need de-grouping * 1W-CRi (read CR, write INT/FP) which needs close inspection * predication types (one using INTs, one using CRs) also some operations i have marked as "R-Type" where they only have one input reg and one output reg (R is actually 2R-1W), ideally a new Form would be created for these. |