Bug 548

Summary:	modify sv_analysis.py to create new svp64 tables
Product:	Libre-SOC's first SoC	Reporter:	Luke Kenneth Casson Leighton <lkcl>
Component:	Specification	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	addw, libre-soc-isa, programmerjake
Priority:	---
Version:	unspecified
Hardware:	Other
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=213
NLnet milestone:	NLNet.2019.10.046.Standards	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
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Description Luke Kenneth Casson Leighton 2020-12-18 00:19:00 GMT

the new svp64 encoding is approaching complete, for review.  with the new RM register maps these need to be applied to instructions, i.e. tables (CSV files) autogenerated.

see https://libre-soc.org/openpower/sv/svp_rewrite/svp64/

requirements: using sv_analysis.py create CSV file, one per Register Profile Type, that map the instruction onto the RM-*-* rypes and associate each register RA RB RC RT RS and BFA etc. with an REXTRA*.

this so that in the PowerDecoder it becomes possible to read those exact same CSV files for creation of the augmented SV ISA.

in addition a "support" page must be created that reads CSV files (see isatsbles.mdwn) and presents the CSV data as wiki tables for easy reading.