Bug 563

Summary:	128-bit instructions and SimpleV
Product:	Libre-SOC's first SoC	Reporter:	Jacob Lifshay <programmerjake>
Component:	Specification	Assignee:	Luke Kenneth Casson Leighton <lkcl>
Status:	CONFIRMED ---
Severity:	enhancement	CC:	libre-soc-isa
Priority:	---
Version:	unspecified
Hardware:	Other
OS:	Linux
See Also:	https://bugs.libre-soc.org/show_bug.cgi?id=562 https://bugs.libre-soc.org/show_bug.cgi?id=535
NLnet milestone:	---	total budget (EUR) for completion of task and all subtasks:	0
budget (EUR) for this task, excluding subtasks' budget:	0	parent task for budget allocation:
child tasks for budget allocation:		The table of payments (in EUR) for this task; TOML format:
Bug Depends on:
Bug Blocks:	213

Description Jacob Lifshay 2020-12-30 19:27:26 GMT

I think we should support 128-bit elements symmetrically to 64/32/16/8-bit operations by just having the 128-bit vsx instruction be the base instruction that gets prefixed, this would mean subvl=1 has 128-bit subvectors, subvl=2 has 256-bit subvectors, 3 for 384-bit, and 4 for 512-bit.

this is because it doesn't make sense to have an instruction for a 64-bit half of a intrinsically 128-bit operation such as f128 add.

Comment 1 Luke Kenneth Casson Leighton 2020-12-30 19:44:34 GMT

conceptually i like it.  especially the symmetry and being able to apply sub-vectoring to 128-bit operations.  it's waaay advanced and in the future though :)

Comment 2 Jacob Lifshay 2020-12-30 19:54:38 GMT

(In reply to Luke Kenneth Casson Leighton from comment #1)
> conceptually i like it.  especially the symmetry and being able to apply
> sub-vectoring to 128-bit operations.  it's waaay advanced and in the future
> though :)

maybe not that far in the future, since aes is a 128-bit operation that we will want to support :)