| Summary: | microwatt SVP64-equivalent of decode1.vhdl to be autogenerated | ||
|---|---|---|---|
| Product: | Libre-SOC Website | Reporter: | Luke Kenneth Casson Leighton <lkcl> |
| Component: | website | Assignee: | Luke Kenneth Casson Leighton <lkcl> |
| Status: | CONFIRMED --- | ||
| Severity: | enhancement | CC: | libre-soc-bugs, paulus |
| Priority: | --- | ||
| Version: | unspecified | ||
| Hardware: | PC | ||
| OS: | Linux | ||
| URL: | https://libre-soc.org/openpower/sv/implementation/ | ||
| NLnet milestone: | --- | total budget (EUR) for completion of task and all subtasks: | 0 |
| budget (EUR) for this task, excluding subtasks' budget: | 0 | parent task for budget allocation: | |
| child tasks for budget allocation: | The table of payments (in EUR) for this task; TOML format: | ||
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Description
Luke Kenneth Casson Leighton
2021-01-28 15:58:25 GMT
started here: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD preliminary output here (pending data structures / types) https://ftp.libre-soc.org/sv_decode.vhdl it should match precisely with the array lengths from decode1.vhdl, and the idea is that in decode2.vhdl wherever a decode_rom_t is used then a corresponding sv_decode_rom_t is also used. if there is no entry and yet the instruction is SVP64-prefixed then an illegal instruction exception must be raised. cross-reference discussion http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/2021-February/000247.html that was an alteration to sv_analysis.py to, instead of having a series of register names that are hard to look up, match up with decode1.vhdl in1/2/3 and make it easy to identify. commit 00c03aad232bdfb4cf20d6afec12247b91105f97 (HEAD -> master, origin/master, origin/HEAD) Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net> Date: Thu Mar 18 12:36:46 2021 +0000 update microwatt sv_decode.vhdl prototype with new sv_out2 column https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=00c03aad232bdfb4cf20d6afec12247b91105f97 two changes: 1) the RS has been moved 2) a new "out2" column has been added including which EXTRA2/3 is used to extend it |