Bug 587

Summary: create setvl pseudocode, v3.0B fields, SVL-Form, and csv file
Product: Libre-SOC's first SoC Reporter: Luke Kenneth Casson Leighton <lkcl>
Component: Source CodeAssignee: Luke Kenneth Casson Leighton <lkcl>
Status: IN_PROGRESS ---    
Severity: enhancement CC: libre-soc-bugs, programmerjake
Priority: ---    
Version: unspecified   
Hardware: Other   
OS: Linux   
URL: https://libre-soc.org/openpower/sv/implementation/
See Also: https://bugs.libre-soc.org/show_bug.cgi?id=535
https://bugs.libre-soc.org/show_bug.cgi?id=583
https://bugs.libre-soc.org/show_bug.cgi?id=579
https://bugs.libre-soc.org/show_bug.cgi?id=862
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Bug Depends on: 914    
Bug Blocks:    

Description Luke Kenneth Casson Leighton 2021-01-29 00:14:43 GMT 
quite a lot of ancillary tasks needed to create setvl:

* DONE add an SVL-Form to the wiki fields
* DONE add v3.0B section 1.7 fields
* DONE add a CSV file (opcode 22)
* DONE create some v3.0B pseudocode,
  WIP unit tests
* DONE add enums FU type, SPR numbers (SVSTATE, SVSRR0)

resolve setting SO or not -- bug 914
Comment 1 Luke Kenneth Casson Leighton 2021-01-29 12:17:19 GMT 
commit 23017a47970e7908664056261c3e2836a0257e44 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Fri Jan 29 11:56:35 2021 +0000

    start adding svp64 enums

commit c63a58b326a2b17d617b098261f217409c65402c
Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date:   Fri Jan 29 12:11:17 2021 +0000

    add SV-Form for setvl instruction for Simple-V


lkcl@fizzy:~/src/libresoc/soc/src/soc$ python3 decoder/power_fields.py

Form SVL
        field ms BitRange([(0, 25)])
        field RA BitRange([(0, 11), (1, 12), (2, 13), (3, 14), (4, 15)])
        field Rc BitRange([(0, 31)])
        field RT BitRange([(0, 6), (1, 7), (2, 8), (3, 9), (4, 10)])
        field SVi BitRange([(0, 16), (1, 17), (2, 18), (3, 19), (4, 20), (5, 21)])
        field vs BitRange([(0, 24)])
        field XO BitRange([(0, 26), (1, 27), (2, 28), (3, 29), (4, 30)])

wha-hey!
Comment 2 Jacob Lifshay 2021-01-29 18:07:28 GMT 
(In reply to Luke Kenneth Casson Leighton from comment #1)
> commit 23017a47970e7908664056261c3e2836a0257e44 (HEAD -> master,
> origin/master)
> Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> Date:   Fri Jan 29 11:56:35 2021 +0000
> 
>     start adding svp64 enums
> 
> commit c63a58b326a2b17d617b098261f217409c65402c
> Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> Date:   Fri Jan 29 12:11:17 2021 +0000
> 
>     add SV-Form for setvl instruction for Simple-V
> 
> 
> lkcl@fizzy:~/src/libresoc/soc/src/soc$ python3 decoder/power_fields.py
> 
> Form SVL
>         field ms BitRange([(0, 25)])
>         field RA BitRange([(0, 11), (1, 12), (2, 13), (3, 14), (4, 15)])
>         field Rc BitRange([(0, 31)])
>         field RT BitRange([(0, 6), (1, 7), (2, 8), (3, 9), (4, 10)])
>         field SVi BitRange([(0, 16), (1, 17), (2, 18), (3, 19), (4, 20), (5,
> 21)])
>         field vs BitRange([(0, 24)])
>         field XO BitRange([(0, 26), (1, 27), (2, 28), (3, 29), (4, 30)])
> 
> wha-hey!

Neat!

Though I'd argue that ms shouldn't be a separate field since you want to set MVL every time you set VL.

Also, bits 22 and 23 need some documentation.
Comment 3 Luke Kenneth Casson Leighton 2021-01-29 19:17:24 GMT 
(In reply to Jacob Lifshay from comment #2)

> > wha-hey!
> 
> Neat!

yeh :)  the power_fields.py just reads
http://libre-soc.org/openpower/isatables/fields.txt

which is the sections 1.6 and 1.7 from the v3.0B spec in a machine-readable
format.

> Though I'd argue that ms shouldn't be a separate field since you want to set
> MVL every time you set VL.

ah no.  there's 4 combinations... actually 6 because RA can be zero
which indicates "use the immediate to set VL" and i can intuit/foresee
circumstances where MVL being set to a different value from VL is useful
or necessary.

it's not like RVV where you set one VL and the hardware decides, "yeah i'll
pick a different value".

there's unfortunately not enough room to have 2 sets of 7-bit immediates,
one to set VL the other to set MVL.

> Also, bits 22 and 23 need some documentation.

they're reserved, and in the page https://libre-soc.org/openpower/sv/setvl/
i also just added the descriptions to http://libre-soc.org/openpower/isatables/fields.txt
Comment 5 Luke Kenneth Casson Leighton 2021-03-21 21:54:27 GMT 
i worked out that there is (just about) space to fit setvl into the bitmanip EXT22 sandbox encoding.  XO is set to 0b11110